Catalog
2.5-Gbps DP++ to HDMI 1.3 retimer
Key Features
• DisplayPort Physical Layer Input Port to TMDS Physical Layer Output PortIntegrated TMDS Level Translator With Receiver EqualizationSupports Data Rates up to 2.5 GbpsIntegrated I2C Logic Block for DVI / HDMI Connector RecognitionIntegrated Active I2C BufferEnhanced ESD: 12 kV on all PinsEnhanced Commercial Temperature Range: 0°C to 85°C36 Pin 6 × 6 QFN PackageAPPLICATIONSPersonal Computer MarketDP/TMDS Hardware Key (Dongle)Desktop PCNotebook PCDocking StationStandalone Video CardDisplayPort Physical Layer Input Port to TMDS Physical Layer Output PortIntegrated TMDS Level Translator With Receiver EqualizationSupports Data Rates up to 2.5 GbpsIntegrated I2C Logic Block for DVI / HDMI Connector RecognitionIntegrated Active I2C BufferEnhanced ESD: 12 kV on all PinsEnhanced Commercial Temperature Range: 0°C to 85°C36 Pin 6 × 6 QFN PackageAPPLICATIONSPersonal Computer MarketDP/TMDS Hardware Key (Dongle)Desktop PCNotebook PCDocking StationStandalone Video Card
Description
AI
The SN75DP129 is a Dual-Mode DisplayPort input to Transition-Minimized Differential Signaling (TMDS) output. The TMDS output has a built-in level translator, compliant with Digital Visual Interface 1.0 (DVI) and High Definition Multimedia Interface 1.3 (HDMI) standards. The SN75DP129 is specified up to a maximum data rate of 2.5 Gbps, supporting resolutions greater then 1920 x 1200 or HDTV 12-bit color depth at 1080p (progressive scan).
An integrated Active I2C buffer isolates the capacitive loading of the source system from that of the sink and interconnecting cable. This isolation improves overall signal integrity of the system and provides greater design margin within the source system for DVI / HDMI compliance testing.
A logic block was designed into the SN75DP129 to assist with TMDS connector identification. Through the use of the I2C_EN pin, this logic block can be enabled to indicate the translated port is an HDMI port; therefore legally supporting HDMI content.
The SN75DP129 is a Dual-Mode DisplayPort input to Transition-Minimized Differential Signaling (TMDS) output. The TMDS output has a built-in level translator, compliant with Digital Visual Interface 1.0 (DVI) and High Definition Multimedia Interface 1.3 (HDMI) standards. The SN75DP129 is specified up to a maximum data rate of 2.5 Gbps, supporting resolutions greater then 1920 x 1200 or HDTV 12-bit color depth at 1080p (progressive scan).
An integrated Active I2C buffer isolates the capacitive loading of the source system from that of the sink and interconnecting cable. This isolation improves overall signal integrity of the system and provides greater design margin within the source system for DVI / HDMI compliance testing.
A logic block was designed into the SN75DP129 to assist with TMDS connector identification. Through the use of the I2C_EN pin, this logic block can be enabled to indicate the translated port is an HDMI port; therefore legally supporting HDMI content.
