SN75971BSCSI differential converter-data | Integrated Circuits (ICs) | 1 | Obsolete | The SN75971B SCSI differential converter-data is a 9-channel RS-485 transceiver. When used in conjunction with its companion control transceiver, the SN75970B, the resulting chip set provides the superior electrical performance of differential SCSI from a single-ended SCSI bus or controller. A 16-bit Ultra-SCSI (or Fast-20) SCSI bus can be implemented with just three devices (two data and one control) in the space efficient, 56-pin, shrink small-outline package (SSOP) or thin shink small outline package (TSSOP) and a few external components. An 8-bit SCSI bus requires only one data and one control transceiver.
The SN75971B is available in a B2 (20 Mxfer) version and a B1 (10 Mxfer) version.
In a typical differential SCSI node, the SCSI controller provides an enable for each external RS-485 transceiver channel. This could require as many as 27
extra terminals for a 16-bit differential bus controller or relegate a 16-bit, single-ended controller to only an 8-bit differential bus. Using the standard nine SCSIcontrol signals, the SN75970B control transceiver decodes the state of the bus and enables the SN75971B data transceiver to transmit the single-ended SCSI input signals (A side) differentially to the cable or receive the differential cable signals (B side) and drive the single-ended outputs to the controller.
A reset function, which disables all outputs and clears internal latches, can be accomplished from two external inputs and two internally-generated signals. RESET\ (reset) and DSENS (differential sense) are available to external circuits for a bus reset or to disable all outputs should a single-ended cable be inadvertently connected to a differential connector. Internally-generated power-up and thermal-shutdown signals have the same affect when the supply voltage is below approximately 3.5 V or the junction temperature exceeds 175°C.
The SCSI, differential, converter-data chip operates in two modes depending on the state of the DRVBUS input. With DRVBUS low, a bidirectional latch circuit sets the direction of data transfer. Each data bit has its own latch, and each bit's direction is independent of all other bits. When neither the single-ended nor the differential sides are asserted, the latch disables both A- and B-side output drivers. When the input to either side is asserted, the latch enables the opposite side's driver and sets data flow from the asserted input to the opposite side of the device. When the input deasserts, the latch maintains the direction until the receiver on the enabled driver detects a deassertion. The latch then returns to the initial state. No parity checking is done by this device; the parity signal passes through the device like other data signals do.
When DRVBUS is high, direction is determined by the SDB signal. However, a change in SDB does not always immediately change the direction. When DRVBUS first asserts, the direction indicated by SDB is latched and takes effect immediately. When SDB changes while DRVBUS is high, the drivers that were on immediately turn off. However, the other driver set does not turn on until the receivers sense a deasserted state on all nine data lines. This is done to prevent the active drivers from turning on until all other drivers are off and the terminators pull the lines to a deasserted state.
The single-ended SCSI bus interface consists of CMOS, bidirectional inputs and outputs. The drivers are rated to ±16 mA of output current. The receiver inputs are pulled high with approximately 4 mA to eliminate the need for external pullup resistors for the open-drain outputs of most single-ended SCSI controllers. The single-ended side of the device is not intended to drive the SCSI bus directly.
The differential SCSI bus interface consists of bipolar, bidirectional inputs and outputs that meet or exceed the requirements of EIA-485 and ISO 8482-1982/TIA TR30.2 referenced by American National Standard of Information Systems (ANSI) X3.131-1994 Small Computer System Interface-2 (SCSI-2) and SCSI-3 Fast-20 Parallel Interface (Fast-20) X3.277:1996.
The SN75971B is characterized for operation over the temperature range of 0°C to 70°C.
The SN75971B SCSI differential converter-data is a 9-channel RS-485 transceiver. When used in conjunction with its companion control transceiver, the SN75970B, the resulting chip set provides the superior electrical performance of differential SCSI from a single-ended SCSI bus or controller. A 16-bit Ultra-SCSI (or Fast-20) SCSI bus can be implemented with just three devices (two data and one control) in the space efficient, 56-pin, shrink small-outline package (SSOP) or thin shink small outline package (TSSOP) and a few external components. An 8-bit SCSI bus requires only one data and one control transceiver.
The SN75971B is available in a B2 (20 Mxfer) version and a B1 (10 Mxfer) version.
In a typical differential SCSI node, the SCSI controller provides an enable for each external RS-485 transceiver channel. This could require as many as 27
extra terminals for a 16-bit differential bus controller or relegate a 16-bit, single-ended controller to only an 8-bit differential bus. Using the standard nine SCSIcontrol signals, the SN75970B control transceiver decodes the state of the bus and enables the SN75971B data transceiver to transmit the single-ended SCSI input signals (A side) differentially to the cable or receive the differential cable signals (B side) and drive the single-ended outputs to the controller.
A reset function, which disables all outputs and clears internal latches, can be accomplished from two external inputs and two internally-generated signals. RESET\ (reset) and DSENS (differential sense) are available to external circuits for a bus reset or to disable all outputs should a single-ended cable be inadvertently connected to a differential connector. Internally-generated power-up and thermal-shutdown signals have the same affect when the supply voltage is below approximately 3.5 V or the junction temperature exceeds 175°C.
The SCSI, differential, converter-data chip operates in two modes depending on the state of the DRVBUS input. With DRVBUS low, a bidirectional latch circuit sets the direction of data transfer. Each data bit has its own latch, and each bit's direction is independent of all other bits. When neither the single-ended nor the differential sides are asserted, the latch disables both A- and B-side output drivers. When the input to either side is asserted, the latch enables the opposite side's driver and sets data flow from the asserted input to the opposite side of the device. When the input deasserts, the latch maintains the direction until the receiver on the enabled driver detects a deassertion. The latch then returns to the initial state. No parity checking is done by this device; the parity signal passes through the device like other data signals do.
When DRVBUS is high, direction is determined by the SDB signal. However, a change in SDB does not always immediately change the direction. When DRVBUS first asserts, the direction indicated by SDB is latched and takes effect immediately. When SDB changes while DRVBUS is high, the drivers that were on immediately turn off. However, the other driver set does not turn on until the receivers sense a deasserted state on all nine data lines. This is done to prevent the active drivers from turning on until all other drivers are off and the terminators pull the lines to a deasserted state.
The single-ended SCSI bus interface consists of CMOS, bidirectional inputs and outputs. The drivers are rated to ±16 mA of output current. The receiver inputs are pulled high with approximately 4 mA to eliminate the need for external pullup resistors for the open-drain outputs of most single-ended SCSI controllers. The single-ended side of the device is not intended to drive the SCSI bus directly.
The differential SCSI bus interface consists of bipolar, bidirectional inputs and outputs that meet or exceed the requirements of EIA-485 and ISO 8482-1982/TIA TR30.2 referenced by American National Standard of Information Systems (ANSI) X3.131-1994 Small Computer System Interface-2 (SCSI-2) and SCSI-3 Fast-20 Parallel Interface (Fast-20) X3.277:1996.
The SN75971B is characterized for operation over the temperature range of 0°C to 70°C. |
SN75976A-EPEnhanced Product 9 Channel Differential Transceiver | Drivers, Receivers, Transceivers | 6 | Active | The SN75976A is an improved replacement for the industry's first 9-channel RS-485 transceiver -- the SN75LBC976. The A version offers improved switching performance, a smaller package, and higher ESD protection. The SN75976A is offered in two versions. The '976A2 skew limits of 4 ns for the differential drivers and 5 ns for the differential receivers complies with the recommended skew budget of the Fast-20 SCSI standard for data transfer rates up to 20 million transfers per second. The '976A1 supports the Fast SCSI skew budget for 10 million transfers per second. The skew limit ensures that the propagation delay times, not only from channel-to-channel but from device-to-device, are closely matched for the tight skew budgets associated with high-speed parallel data buses.
The patented thermal enhancements made to the 56-pin shrink small-outline package (SSOP) of the SN75976 have been applied to the new, thin shrink, small-outline package (TSSOP). The TSSOP package offers even less board area requirements than the SSOP while reducing the package height to 1 mm. This provides more board area and allows component mounting to both sides of the printed circuit boards for low-profile, space-restricted applications such as small form-factor hard disk drives.
In addition to speed improvements, the '976A can withstand electrostatic discharges exceeding 12 kV using the human-body model, and 600 V using the machine model of MIL-PRF-38535, Method 3015.7 on the RS-485 I/O terminals. This is six times the industry standard and provides protection from the noise that can be coupled into external cables. The other terminals of the device can withstand discharges exceeding 4 kV and 400 V respectively.
Each of the nine channels of the '976A typically meet or exceed the requirements of EIA RS-485 (1983) and ISO8482-1987/TIA TR30.2 referenced by American National Standard of Information (ANSI) Systems, X3.131-1994 (SCSI-2) standard, X2.277-1996 (Fast-20 Parallel Interface), and the Intelligent Peripheral Interface Physical Layer-ANSI X3.129-1986 standard.
The SN75976A is characterized for operation over an ambient air temperature range of 0°C to 70°C. The SN55976A is characterized for operation over an ambient air temperature range of -55°C to 125°C.
The SN75976A is an improved replacement for the industry's first 9-channel RS-485 transceiver -- the SN75LBC976. The A version offers improved switching performance, a smaller package, and higher ESD protection. The SN75976A is offered in two versions. The '976A2 skew limits of 4 ns for the differential drivers and 5 ns for the differential receivers complies with the recommended skew budget of the Fast-20 SCSI standard for data transfer rates up to 20 million transfers per second. The '976A1 supports the Fast SCSI skew budget for 10 million transfers per second. The skew limit ensures that the propagation delay times, not only from channel-to-channel but from device-to-device, are closely matched for the tight skew budgets associated with high-speed parallel data buses.
The patented thermal enhancements made to the 56-pin shrink small-outline package (SSOP) of the SN75976 have been applied to the new, thin shrink, small-outline package (TSSOP). The TSSOP package offers even less board area requirements than the SSOP while reducing the package height to 1 mm. This provides more board area and allows component mounting to both sides of the printed circuit boards for low-profile, space-restricted applications such as small form-factor hard disk drives.
In addition to speed improvements, the '976A can withstand electrostatic discharges exceeding 12 kV using the human-body model, and 600 V using the machine model of MIL-PRF-38535, Method 3015.7 on the RS-485 I/O terminals. This is six times the industry standard and provides protection from the noise that can be coupled into external cables. The other terminals of the device can withstand discharges exceeding 4 kV and 400 V respectively.
Each of the nine channels of the '976A typically meet or exceed the requirements of EIA RS-485 (1983) and ISO8482-1987/TIA TR30.2 referenced by American National Standard of Information (ANSI) Systems, X3.131-1994 (SCSI-2) standard, X2.277-1996 (Fast-20 Parallel Interface), and the Intelligent Peripheral Interface Physical Layer-ANSI X3.129-1986 standard.
The SN75976A is characterized for operation over an ambient air temperature range of 0°C to 70°C. The SN55976A is characterized for operation over an ambient air temperature range of -55°C to 125°C. |
| Drivers, Receivers, Transceivers | 6 | Active | |
SN75ALS057Trapezoidal-Waveform Interface Bus Transceiver | Interface | 2 | Active | The SN75ALS056 is an eight-channel, monolithic, high-speed, advanced low-power Schottky (ALS) device designed for two-way data communication in a densely populated backplane. The SN75ALS057 is a four-channel version with independent driver-input (Dn) and receiver-output (Rn) pins and a separate driver disable for each driver (En).
These transceivers feature open-collector driver outputs with series Schottky diodes to reduce capacitive loading to the bus. By using a 2-V pullup termination on the bus, the output signal swing is approximately 1 V, which reduces the power necessary to drive the bus load capacitance. The driver outputs generate trapezoidal waveforms that reduce crosstalk between channels. The drivers are capable of driving an equivalent dc load as low as 18.5. The receivers have internal low-pass filters to further improve noise immunity.
The SN75ALS056 and SN75ALS057 are characterized for operation from 0°C to 70°C.
The SN75ALS056 is an eight-channel, monolithic, high-speed, advanced low-power Schottky (ALS) device designed for two-way data communication in a densely populated backplane. The SN75ALS057 is a four-channel version with independent driver-input (Dn) and receiver-output (Rn) pins and a separate driver disable for each driver (En).
These transceivers feature open-collector driver outputs with series Schottky diodes to reduce capacitive loading to the bus. By using a 2-V pullup termination on the bus, the output signal swing is approximately 1 V, which reduces the power necessary to drive the bus load capacitance. The driver outputs generate trapezoidal waveforms that reduce crosstalk between channels. The drivers are capable of driving an equivalent dc load as low as 18.5. The receivers have internal low-pass filters to further improve noise immunity.
The SN75ALS056 and SN75ALS057 are characterized for operation from 0°C to 70°C. |
SN75ALS085LAN access unit interface dual driver & receiver | Interface | 1 | Obsolete | The SN75ALS085 is a high-speed, advanced low-power Schottky, dual-channel driver/receiver device designed for use in the AUI of ANSI/IEEE Std 802.3-1988. The two drivers on the device drive a 78-balanced, terminated twisted-pair transmission line up to a maximum length of 50 meters. In the off (idle) state, the drivers maintain minimal differential output voltage on the twisted-pair line and, at the same time, remain within the required output common-mode range.
With the driver enable (TXEN) high, upon receiving the first falling edge into the driver input, the differential outputs rise to full-amplitude output levels within 25 ns. The output amplitude is maintained for the remainder of the packet. After the last positive packet edge is transmitted into the driver, the driver maintains a minimum of 70% full differential output for a minimum of 200 ns, then decays to a minimum level for the reset (idle) condition within 8 us. Disabling the driver by taking the driver enable low also forces the output into the idle condition after the normal 8-us timeout. While operating, the drivers are able to withstand a set of fault conditions and not suffer damage due to the faults being applied. The drivers power up in the idle state to ensure that no activity is placed on the twisted-pair cable, which could be interpreted as network traffic.
The line receiver squelch function interfaces to a differential twisted-pair line terminated external to the device. The receiver squelch circuit allows differential receive signals to pass through, as long as the input amplitude and pulse duration are greater than the minimum squelch threshold. This ensures a good signal-to-noise ratio while the data path is active and prevents system noise from causing false data transitions during line shutdown and line-idle conditions. The receiver outputs (RXO) default to a high level and the receiver-enable (RXEN) outputs default to a low level while the squelch function is blocking the data path through the receiver (idle). The line receiver squelch becomes active within 50 ns when the input squelch threshold is exceeded. RXEN is driven high when the squelch circuit allows data to pass through the receiver. The receiver squelch circuit also can withstand a set of fault conditions while operating, without causing permanent damage to the device.
The purpose of the loop functions is to provide a means by which system data-path verification can be done to isolate faulty interfaces and assist in network diagnosis. The LOOP pins are TTL compatible and must be held high for normal operation. When LOOP1\ is taken low, the output of driver 1 (TXO1) immediately goes into the idle state. Also, the input to receiver 1 is ignored, and a path from a transmit input (TXI1) to RXO1 is established. When LOOP1\ is taken back high, driver 1 and receiver 1 revert back to their normal operation. When LOOP2\ is taken low, a similar data path is established between TXI1 and RXO2. TXEN1 must be high for the loop functions to operate, and TXEN1 can be used to gate the loop function if desired. During loop operation, the respective RXEN reflects the status of TXEN1.
The SN75ALS085 is characterized for operation from 0°C to 70°C.
The SN75ALS085 is a high-speed, advanced low-power Schottky, dual-channel driver/receiver device designed for use in the AUI of ANSI/IEEE Std 802.3-1988. The two drivers on the device drive a 78-balanced, terminated twisted-pair transmission line up to a maximum length of 50 meters. In the off (idle) state, the drivers maintain minimal differential output voltage on the twisted-pair line and, at the same time, remain within the required output common-mode range.
With the driver enable (TXEN) high, upon receiving the first falling edge into the driver input, the differential outputs rise to full-amplitude output levels within 25 ns. The output amplitude is maintained for the remainder of the packet. After the last positive packet edge is transmitted into the driver, the driver maintains a minimum of 70% full differential output for a minimum of 200 ns, then decays to a minimum level for the reset (idle) condition within 8 us. Disabling the driver by taking the driver enable low also forces the output into the idle condition after the normal 8-us timeout. While operating, the drivers are able to withstand a set of fault conditions and not suffer damage due to the faults being applied. The drivers power up in the idle state to ensure that no activity is placed on the twisted-pair cable, which could be interpreted as network traffic.
The line receiver squelch function interfaces to a differential twisted-pair line terminated external to the device. The receiver squelch circuit allows differential receive signals to pass through, as long as the input amplitude and pulse duration are greater than the minimum squelch threshold. This ensures a good signal-to-noise ratio while the data path is active and prevents system noise from causing false data transitions during line shutdown and line-idle conditions. The receiver outputs (RXO) default to a high level and the receiver-enable (RXEN) outputs default to a low level while the squelch function is blocking the data path through the receiver (idle). The line receiver squelch becomes active within 50 ns when the input squelch threshold is exceeded. RXEN is driven high when the squelch circuit allows data to pass through the receiver. The receiver squelch circuit also can withstand a set of fault conditions while operating, without causing permanent damage to the device.
The purpose of the loop functions is to provide a means by which system data-path verification can be done to isolate faulty interfaces and assist in network diagnosis. The LOOP pins are TTL compatible and must be held high for normal operation. When LOOP1\ is taken low, the output of driver 1 (TXO1) immediately goes into the idle state. Also, the input to receiver 1 is ignored, and a path from a transmit input (TXI1) to RXO1 is established. When LOOP1\ is taken back high, driver 1 and receiver 1 revert back to their normal operation. When LOOP2\ is taken low, a similar data path is established between TXI1 and RXO2. TXEN1 must be high for the loop functions to operate, and TXEN1 can be used to gate the loop function if desired. During loop operation, the respective RXEN reflects the status of TXEN1.
The SN75ALS085 is characterized for operation from 0°C to 70°C. |
| Drivers, Receivers, Transceivers | 2 | Active | The SN75ALS1177 and SN75ALS1178 dual differential drivers and receivers are integrated circuits designed for bidirectional data communication on multipoint bus transmission lines. The devices are designed for balanced transmission lines, and meet standards TIA/EIA-422-B and TIA/EIA-485-A.
The SN75ALS1177 combines dual 3-state differential line drivers and dual 3-state differential input line receivers, both of which operate from a single 5V power supply. The drivers and receivers have active-high and active-low enables, respectively, which can be externally connected together to function as direction control. The SN75ALS1178 drivers each have an individual active-high enable. Fail-safe design ensures that when the receiver inputs are open, the receiver outputs are always high.
The SN75ALS1177 and SN75ALS1178 are characterized for operation from 0°C to 70°C.
The SN75ALS1177 and SN75ALS1178 dual differential drivers and receivers are integrated circuits designed for bidirectional data communication on multipoint bus transmission lines. The devices are designed for balanced transmission lines, and meet standards TIA/EIA-422-B and TIA/EIA-485-A.
The SN75ALS1177 combines dual 3-state differential line drivers and dual 3-state differential input line receivers, both of which operate from a single 5V power supply. The drivers and receivers have active-high and active-low enables, respectively, which can be externally connected together to function as direction control. The SN75ALS1178 drivers each have an individual active-high enable. Fail-safe design ensures that when the receiver inputs are open, the receiver outputs are always high.
The SN75ALS1177 and SN75ALS1178 are characterized for operation from 0°C to 70°C. |
| Integrated Circuits (ICs) | 2 | Active | The SN75ALS1177 and SN75ALS1178 dual differential drivers and receivers are integrated circuits designed for bidirectional data communication on multipoint bus transmission lines. The devices are designed for balanced transmission lines, and meet standards TIA/EIA-422-B and TIA/EIA-485-A.
The SN75ALS1177 combines dual 3-state differential line drivers and dual 3-state differential input line receivers, both of which operate from a single 5V power supply. The drivers and receivers have active-high and active-low enables, respectively, which can be externally connected together to function as direction control. The SN75ALS1178 drivers each have an individual active-high enable. Fail-safe design ensures that when the receiver inputs are open, the receiver outputs are always high.
The SN75ALS1177 and SN75ALS1178 are characterized for operation from 0°C to 70°C.
The SN75ALS1177 and SN75ALS1178 dual differential drivers and receivers are integrated circuits designed for bidirectional data communication on multipoint bus transmission lines. The devices are designed for balanced transmission lines, and meet standards TIA/EIA-422-B and TIA/EIA-485-A.
The SN75ALS1177 combines dual 3-state differential line drivers and dual 3-state differential input line receivers, both of which operate from a single 5V power supply. The drivers and receivers have active-high and active-low enables, respectively, which can be externally connected together to function as direction control. The SN75ALS1178 drivers each have an individual active-high enable. Fail-safe design ensures that when the receiver inputs are open, the receiver outputs are always high.
The SN75ALS1177 and SN75ALS1178 are characterized for operation from 0°C to 70°C. |
SN75ALS160Octal General-Purpose Interface Bus Transceiver | Drivers, Receivers, Transceivers | 4 | Active | The SN75ALS160 eight-channel general-purpose interface bus transceivers are monolithic, high-speed, advanced low-power Schottky (ALS) devices designed for two-way data communications over single-ended transmission lines. This device is designed to meet the requirements of IEEE Standard 488-1978. The transceivers feature driver outputs that can be operated in either the passive-pullup or 3-state mode. If talk enable (TE) is high, these ports have the characteristics of passive-pullup outputs when pullup enable (PE) is low and of 3-state outputs when PE is high. Taking TE low places these ports in the high-impedance state. The driver outputs are designed to handle loads up to 48 mA of sink current.
An active turn-off feature has been incorporated into the bus-terminating resistors so that the device exhibits a high impedance to the bus when VCC= 0. When combined with the SN75ALS161 or SN75ALS162 bus management transceiver, the pair provides the complete 16-wire interface for the IEEE-488 bus.
The SN75ALS160 is characterized for operation from 0°C to 70°C.
The SN75ALS160 eight-channel general-purpose interface bus transceivers are monolithic, high-speed, advanced low-power Schottky (ALS) devices designed for two-way data communications over single-ended transmission lines. This device is designed to meet the requirements of IEEE Standard 488-1978. The transceivers feature driver outputs that can be operated in either the passive-pullup or 3-state mode. If talk enable (TE) is high, these ports have the characteristics of passive-pullup outputs when pullup enable (PE) is low and of 3-state outputs when PE is high. Taking TE low places these ports in the high-impedance state. The driver outputs are designed to handle loads up to 48 mA of sink current.
An active turn-off feature has been incorporated into the bus-terminating resistors so that the device exhibits a high impedance to the bus when VCC= 0. When combined with the SN75ALS161 or SN75ALS162 bus management transceiver, the pair provides the complete 16-wire interface for the IEEE-488 bus.
The SN75ALS160 is characterized for operation from 0°C to 70°C. |
SN75ALS161Octal General-Purpose Interface Bus Transceiver | Drivers, Receivers, Transceivers | 5 | Active | The SN75ALS161 eight-channel general-purpose interface bus transceivers are high-speed, advanced low-power Schottky-process devices designed to provide the bus-management and data-transfer signals between operating units of a single-controller instrumentation system. When combined with the SN75ALS160 octal bus transceivers, this device provides a complete 16-wire interface for the IEEE 488 bus.
The SN75ALS161 device features eight driver-receiver pairs connected in a front-to-back configuration to form input/output (I/O) ports at both the bus and terminal sides. The direction of data through these driver-receiver pairs is determined by the direction-control (DC) and talk-enable (TE) signals.
The driver outputs general-purpose interface bus (GPIB I/O ports) feature active bus-terminating resistor circuits designed to provide a high impedance to the bus when VCC= 0. The drivers are designed to handle sink-current loads up to 48 mA. Each receiver features pnp transistor inputs for high input impedance and hysteresis of 400 mV on the commercial part, and 250 mV on the military part, minimum, for increased noise immunity. All receivers have 3-state outputs, to present a high impedance to the terminal when disabled.
The SN75ALS161 is characterized for operation from 0°C to 70°C.
The SN75ALS161 eight-channel general-purpose interface bus transceivers are high-speed, advanced low-power Schottky-process devices designed to provide the bus-management and data-transfer signals between operating units of a single-controller instrumentation system. When combined with the SN75ALS160 octal bus transceivers, this device provides a complete 16-wire interface for the IEEE 488 bus.
The SN75ALS161 device features eight driver-receiver pairs connected in a front-to-back configuration to form input/output (I/O) ports at both the bus and terminal sides. The direction of data through these driver-receiver pairs is determined by the direction-control (DC) and talk-enable (TE) signals.
The driver outputs general-purpose interface bus (GPIB I/O ports) feature active bus-terminating resistor circuits designed to provide a high impedance to the bus when VCC= 0. The drivers are designed to handle sink-current loads up to 48 mA. Each receiver features pnp transistor inputs for high input impedance and hysteresis of 400 mV on the commercial part, and 250 mV on the military part, minimum, for increased noise immunity. All receivers have 3-state outputs, to present a high impedance to the terminal when disabled.
The SN75ALS161 is characterized for operation from 0°C to 70°C. |
SN75ALS162Octal General-Purpose Interface Bus Transceiver | Drivers, Receivers, Transceivers | 2 | Active | The SN75ALS162 eight-channel general-purpose interface bus (GPIB) transceiver is a monolithic, high-speed, advanced low-power Schottky process device designed to provide the bus-management and data-transfer signals between operating units of a multiple-controller instrumentation system. When combined with the SN75ALS160 octal bus transceiver, the SN75ALS162 provides the complete 16-wire interface for the IEEE 488 bus.
The SN75ALS162 features eight driver-receiver pairs connected in a front-to-back configuration to form input/output (I/O) ports at both the bus and terminal sides. The direction of data through these driver-receiver pairs is determined by the DC, TE, and SC enable signals. The SC input allows the REN and IFC transceivers to be controlled independently.
The driver outputs (GPIB I/O ports) feature active bus-terminating resistor circuits designed to provide a high impedance to the bus when VCC= 0. The drivers are designed to handle loads up to 48 mA of sink current. Each receiver features pnp transistor inputs for high input impedance and hysteresis of 400 mV minimum for increased noise immunity. All receivers have 3-state outputs to present a high impedance to the terminal when disabled.
The SN75ALS162 is characterized for operation from 0°C to 70°C.
H = high level, L = low level, R = receive, T = transmit, X = irrelevant
Direction of data transmission is from the terminal side to the bus side, and the direction of data receiving is from the bus side to the terminal side.
Data transfer is noninverting in both directions.
ATN is a normal transceiver channel that functions additionally as an internal direction control or talk enable for EOI whenever the DC and TE inputs are in the same state. When DC and TE are in opposite states, the ATN channel functions as an independent transceiver only.
The SN75ALS162 eight-channel general-purpose interface bus (GPIB) transceiver is a monolithic, high-speed, advanced low-power Schottky process device designed to provide the bus-management and data-transfer signals between operating units of a multiple-controller instrumentation system. When combined with the SN75ALS160 octal bus transceiver, the SN75ALS162 provides the complete 16-wire interface for the IEEE 488 bus.
The SN75ALS162 features eight driver-receiver pairs connected in a front-to-back configuration to form input/output (I/O) ports at both the bus and terminal sides. The direction of data through these driver-receiver pairs is determined by the DC, TE, and SC enable signals. The SC input allows the REN and IFC transceivers to be controlled independently.
The driver outputs (GPIB I/O ports) feature active bus-terminating resistor circuits designed to provide a high impedance to the bus when VCC= 0. The drivers are designed to handle loads up to 48 mA of sink current. Each receiver features pnp transistor inputs for high input impedance and hysteresis of 400 mV minimum for increased noise immunity. All receivers have 3-state outputs to present a high impedance to the terminal when disabled.
The SN75ALS162 is characterized for operation from 0°C to 70°C.
H = high level, L = low level, R = receive, T = transmit, X = irrelevant
Direction of data transmission is from the terminal side to the bus side, and the direction of data receiving is from the bus side to the terminal side.
Data transfer is noninverting in both directions.
ATN is a normal transceiver channel that functions additionally as an internal direction control or talk enable for EOI whenever the DC and TE inputs are in the same state. When DC and TE are in opposite states, the ATN channel functions as an independent transceiver only. |
