SN74S112A Series

Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset

Catalog

Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset

Part	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Output Type	Mounting Type	Supplier Device Package	Clock Frequency	Type	Function	Voltage - Supply [Min]	Voltage - Supply [Max]	Operating Temperature [Max]	Max Propagation Delay @ V, Max CL	Current - Quiescent (Iq)	Number of Bits per Element	Number of Elements	Trigger Type	Package / Case	Package / Case	Package / Case	Package / Case [x]	Package / Case [y]
Texas Instruments SN74S112AN	1 mA	20 mA	Complementary	Through Hole	16-PDIP	125 MHz	JK Type	Reset Set(Preset)	4.75 V	5.25 V	70 °C	7 ns	252 mA	1	2	Negative Edge	0.3 in	16-DIP	7.62 mm
Texas Instruments SN74S112ADR	1 mA	20 mA	Complementary	Surface Mount	16-SOIC	125 MHz	JK Type	Reset Set(Preset)	4.75 V	5.25 V	70 °C	7 ns		1	2	Negative Edge		16-SOIC		0.154 in	3.9 mm
Texas Instruments SN74S112AN3	1 mA	20 mA	Complementary	Through Hole	16-PDIP	125 MHz	JK Type	Reset Set(Preset)	4.75 V	5.25 V	70 °C	7 ns	252 mA	1	2	Negative Edge	0.3 in	16-DIP	7.62 mm

Catalog

Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset

Key Features

• Fully Buffered to Offer Maximum Isolation from External DisturbancePackage Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPsDependable Texas Instruments Quality and ReliabilityFully Buffered to Offer Maximum Isolation from External DisturbancePackage Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPsDependable Texas Instruments Quality and Reliability

Description

These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset and clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high. The SN54LS112A and SN54S112 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LS112A and SN74S112A are characterized for operation from 0°C to 70°C. These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset and clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high. The SN54LS112A and SN54S112 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LS112A and SN74S112A are characterized for operation from 0°C to 70°C.