Texas Instruments

The ’LVTH16501 devices are 18-bit universal bus transceivers designed for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. Data flow in each direction is controlled by output-enable (OEAB andOEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the devices operate in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is high, the outputs are active. When OEAB is low, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B but usesOEBA, LEBA, and CLKBA. The output enables are complementary (OEAB is active high andOEBAis active low). Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. When VCCis between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V,OEshould be tied to VCCthrough a pullup resistor and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. These devices are fully specified for hot-insertion applications using Ioffand power-up 3-state. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The ’LVTH16501 devices are 18-bit universal bus transceivers designed for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. Data flow in each direction is controlled by output-enable (OEAB andOEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the devices operate in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is high, the outputs are active. When OEAB is low, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B but usesOEBA, LEBA, and CLKBA. The output enables are complementary (OEAB is active high andOEBAis active low). Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. When VCCis between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V,OEshould be tied to VCCthrough a pullup resistor and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. These devices are fully specified for hot-insertion applications using Ioffand power-up 3-state. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

These 16-bit buffers/drivers are designed specifically for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. These devices are noninverting 16-bit buffers composed of two 8-bit sections with separate output-enable signals. For either 8-bit buffer section, the two output-enable (1OE1and 1OE2or 2OE1and 2OE2) inputs must be low for the corresponding Y outputs to be active. If either output-enable input is high, the outputs of that 8-bit buffer section are in the high-impedance state. When VCCis between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. These devices are fully specified for hot-insertion applications using Ioffand power-up 3-state. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The SN54LVTH16541 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LVTH16541 is characterized for operation from -40°C to 85°C. These 16-bit buffers/drivers are designed specifically for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. These devices are noninverting 16-bit buffers composed of two 8-bit sections with separate output-enable signals. For either 8-bit buffer section, the two output-enable (1OE1and 1OE2or 2OE1and 2OE2) inputs must be low for the corresponding Y outputs to be active. If either output-enable input is high, the outputs of that 8-bit buffer section are in the high-impedance state. When VCCis between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. These devices are fully specified for hot-insertion applications using Ioffand power-up 3-state. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The SN54LVTH16541 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LVTH16541 is characterized for operation from -40°C to 85°C.

The 'LVTH16543 devices are 16-bit registered transceivers designed for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. These devices can be used as two 8-bit transceivers or one 16-bit transceiver. Separate latch-enable (LEAB\ or LEBA\) and output-enable (OEAB\ or OEBA\) inputs are provided for each register to permit independent control in either direction of data flow. The A-to-B enable (CEAB\) input must be low to enter data from A or to output data from B. If CEAB\ is low and LEAB\ is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB\ puts the A latches in the storage mode. With CEAB\ and OEAB\ both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar but requires using the CEBA\, LEBA\, and OEBA\ inputs. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. When VCCis between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. These devices are fully specified for hot-insertion applications using Ioffand power-up 3-state. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The SN54LVTH16543 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LVTH16543 is characterized for operation from -40°C to 85°C. The 'LVTH16543 devices are 16-bit registered transceivers designed for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. These devices can be used as two 8-bit transceivers or one 16-bit transceiver. Separate latch-enable (LEAB\ or LEBA\) and output-enable (OEAB\ or OEBA\) inputs are provided for each register to permit independent control in either direction of data flow. The A-to-B enable (CEAB\) input must be low to enter data from A or to output data from B. If CEAB\ is low and LEAB\ is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB\ puts the A latches in the storage mode. With CEAB\ and OEAB\ both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar but requires using the CEBA\, LEBA\, and OEBA\ inputs. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. When VCCis between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. These devices are fully specified for hot-insertion applications using Ioffand power-up 3-state. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The SN54LVTH16543 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LVTH16543 is characterized for operation from -40°C to 85°C.

The SN74LVTH16543 is a 16–bit registered transceiver designed for low–voltage (3.3–V) VCCoperation, but with the capability to provide a TTL interface to a 5–V system environment. This device can be used as two 8–bit transceivers or one 16–bit transceiver. Separate latch–enable (LEABorLEBA) and output–enable (OEABorOEBA) inputs are provided for each register to permit independent control in either direction of data flow. The A–to–B enable (CEAB) input must be low to enter data from A or to output data from B. IfCEABis low andLEABis low, the A–to–B latches are transparent; a subsequent low–to–high transition ofLEABputs the A latches in the storage mode. WithCEABandOEABboth low, the 3–state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar, but requires using theCEBA,LEBA, andOEBAinputs. Active bus–hold circuitry is provided to hold unused or floating data inputs at a valid logic level. When VCCis between 0 and 1.5 V, the device is in the high–impedance state during power up or power down. However, to ensure the high–impedance state above 1.5 V,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current–sinking capability of the driver. This device is fully specified for hot–insertion applications using Ioffand power–up 3–state. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power–up 3–state circuitry places the outputs in the high–impedance state during power up and power down, which prevents driver conflict. The SN74LVTH16543 is a 16–bit registered transceiver designed for low–voltage (3.3–V) VCCoperation, but with the capability to provide a TTL interface to a 5–V system environment. This device can be used as two 8–bit transceivers or one 16–bit transceiver. Separate latch–enable (LEABorLEBA) and output–enable (OEABorOEBA) inputs are provided for each register to permit independent control in either direction of data flow. The A–to–B enable (CEAB) input must be low to enter data from A or to output data from B. IfCEABis low andLEABis low, the A–to–B latches are transparent; a subsequent low–to–high transition ofLEABputs the A latches in the storage mode. WithCEABandOEABboth low, the 3–state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar, but requires using theCEBA,LEBA, andOEBAinputs. Active bus–hold circuitry is provided to hold unused or floating data inputs at a valid logic level. When VCCis between 0 and 1.5 V, the device is in the high–impedance state during power up or power down. However, to ensure the high–impedance state above 1.5 V,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current–sinking capability of the driver. This device is fully specified for hot–insertion applications using Ioffand power–up 3–state. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power–up 3–state circuitry places the outputs in the high–impedance state during power up and power down, which prevents driver conflict.

The 'LVTH16646 devices are 16-bit bus transceivers designed for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. These devices can be used as two 8-bit transceivers or one 16-bit transceiver. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the 'LVTH16646 devices. Output-enable (OE\) and direction-control (DIR) inputs are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either register or in both. The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. DIR determines which bus receives data when OE\ is low. In the isolation mode (OE\ high), A data can be stored in one register and/or B data can be stored in the other register. When an output function is disabled, the input function is still enabled and can be used to store and transmit data. Only one of the two buses, A or B, can be driven at a time. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. These devices are fully specified for hot-insertion applications using Ioffand power-up 3-state. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The 'LVTH16646 devices are 16-bit bus transceivers designed for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. These devices can be used as two 8-bit transceivers or one 16-bit transceiver. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the 'LVTH16646 devices. Output-enable (OE\) and direction-control (DIR) inputs are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either register or in both. The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. DIR determines which bus receives data when OE\ is low. In the isolation mode (OE\ high), A data can be stored in one register and/or B data can be stored in the other register. When an output function is disabled, the input function is still enabled and can be used to store and transmit data. Only one of the two buses, A or B, can be driven at a time. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. These devices are fully specified for hot-insertion applications using Ioffand power-up 3-state. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

The 'LVTH16652 devices are 16-bit bus transceivers designed for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. These devices can be used as two 8-bit transceivers or one 16-bit transceiver. Output-enable (OEAB and OEBA\) inputs are provided to control the transceiver functions. Select-control (SAB and SBA) inputs are provided to select whether real-time or stored data is transferred. A low input level selects real-time data, and a high input level selects stored data. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the 'LVTH16652 devices. Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the appropriate clock (CLKAB or CLKBA) inputs, regardless of the levels on the select-control or output-enable inputs. When SAB and SBA are in the real-time transfer mode, it also is possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA\. In this configuration, each output reinforces its input. When all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last level configuration. When VCCis between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE\ should be tied to VCCthrough a pullup resistor and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. These devices are fully specified for hot-insertion applications using Ioffand power-up 3-state. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The SN54LVTH16652 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LVTH16652 is characterized for operation from -40°C to 85°C. The 'LVTH16652 devices are 16-bit bus transceivers designed for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. These devices can be used as two 8-bit transceivers or one 16-bit transceiver. Output-enable (OEAB and OEBA\) inputs are provided to control the transceiver functions. Select-control (SAB and SBA) inputs are provided to select whether real-time or stored data is transferred. A low input level selects real-time data, and a high input level selects stored data. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the 'LVTH16652 devices. Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the appropriate clock (CLKAB or CLKBA) inputs, regardless of the levels on the select-control or output-enable inputs. When SAB and SBA are in the real-time transfer mode, it also is possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA\. In this configuration, each output reinforces its input. When all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last level configuration. When VCCis between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE\ should be tied to VCCthrough a pullup resistor and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. These devices are fully specified for hot-insertion applications using Ioffand power-up 3-state. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The SN54LVTH16652 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LVTH16652 is characterized for operation from -40°C to 85°C.

The SN74LVTH16652 is a 16-bit bus transceiver designed for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. These devices can be used as two 8-bit transceivers or one 16-bit transceiver. Output-enable (OEAB and OEBA\) inputs are provided to control the transceiver functions. Select-control (SAB and SBA) inputs are provided to select whether real-time or stored data is transferred. A low input level selects real-time data, and a high input level selects stored data. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the SN74LVTH16652. Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the appropriate clock (CLKAB or CLKBA) inputs, regardless of the levels on the select-control or output-enable inputs. When SAB and SBA are in the real-time transfer mode, it also is possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA\. In this configuration, each output reinforces its input. When all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last level configuration. When VCCis between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE\ should be tied to VCCthrough a pullup resistor, and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. This device is fully specified for hot-insertion applications using Ioffand power-up 3-state. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The SN74LVTH16652 is a 16-bit bus transceiver designed for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. These devices can be used as two 8-bit transceivers or one 16-bit transceiver. Output-enable (OEAB and OEBA\) inputs are provided to control the transceiver functions. Select-control (SAB and SBA) inputs are provided to select whether real-time or stored data is transferred. A low input level selects real-time data, and a high input level selects stored data. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the SN74LVTH16652. Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the appropriate clock (CLKAB or CLKBA) inputs, regardless of the levels on the select-control or output-enable inputs. When SAB and SBA are in the real-time transfer mode, it also is possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA\. In this configuration, each output reinforces its input. When all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last level configuration. When VCCis between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE\ should be tied to VCCthrough a pullup resistor, and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. This device is fully specified for hot-insertion applications using Ioffand power-up 3-state. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

The 'LVTH16835 devices are 18-bit universal bus drivers designed for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. Data flow from A to Y is controlled by the output-enable (OE\) input. These devices operate in the transparent mode when the latch-enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of the clock. When OE\ is high, the outputs are in the high-impedance state. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. When VCCis between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. These devices are fully specified for hot-insertion applications using Ioffand power-up 3-state. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The SN54LVTH16835 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LVTH16835 is characterized for operation from -40°C to 85°C. The 'LVTH16835 devices are 18-bit universal bus drivers designed for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. Data flow from A to Y is controlled by the output-enable (OE\) input. These devices operate in the transparent mode when the latch-enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of the clock. When OE\ is high, the outputs are in the high-impedance state. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. When VCCis between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. These devices are fully specified for hot-insertion applications using Ioffand power-up 3-state. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The SN54LVTH16835 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LVTH16835 is characterized for operation from -40°C to 85°C.

The 'LVTH16952 devices are 16-bit registered transceivers designed for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. These devices can be used as two 8-bit transceivers or one 16-bit transceiver. Data on the A or B bus is stored in the registers on the low-to-high transition of the clock (CLKAB or CLKBA) input, provided that the clock-enable (CLKENAB\ or CLKENBA\) input is low. Taking the output-enable (OEAB\ or OEBA\) input low accesses the data on either port. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. When VCCis between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. These devices are fully specified for hot-insertion applications using Ioffand power-up 3-state. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The SN54LVTH16952 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LVTH16952 is characterized for operation from -40°C to 85°C. The 'LVTH16952 devices are 16-bit registered transceivers designed for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. These devices can be used as two 8-bit transceivers or one 16-bit transceiver. Data on the A or B bus is stored in the registers on the low-to-high transition of the clock (CLKAB or CLKBA) input, provided that the clock-enable (CLKENAB\ or CLKENBA\) input is low. Taking the output-enable (OEAB\ or OEBA\) input low accesses the data on either port. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. When VCCis between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. These devices are fully specified for hot-insertion applications using Ioffand power-up 3-state. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The SN54LVTH16952 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LVTH16952 is characterized for operation from -40°C to 85°C.

The ’LVTH18502A and ’LVTH182502A scan test devices with 18-bit universal bus transceivers are members of the Texas Instruments SCOPE™ testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface. Additionally, these devices are designed specifically for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. In the normal mode, these devices are 18-bit universal bus transceivers, that combine with D-type latches and D-type flip-flops, they allow data to flow in the transparent, latched, or clocked modes. Another use is as two 9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPE universal bus transceivers. Data flow in each direction is controlled by output-enable (OEAB\ and OEBA\), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A-bus data is latched while CLKAB is held at a static low or high logic level. Otherwise, if LEAB is low, A-bus data is stored on a low-to-high transition of CLKAB. When OEAB\ is low, the B outputs are active. When OEAB\ is high, the B outputs are in the high-impedance state. B-to-A data flow is similar to A-to-B data flow, but uses the OEBA\, LEBA, and CLKBA inputs. In the test mode, the normal operation of the SCOPE universal bus transceivers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990. Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudorandom pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The B-port outputs of ’LVTH182502A, which are designed to source or sink up to 12 mA, include 25-series resistors to reduce overshoot and undershoot. The SN54LVTH18502A and SN54LVTH182502A are characterized for operation over the full military temperature range of –55°C to 125°C. The SN74LVTH18502A and SN74LVTH182502A are characterized for operation from –40°C to 85°C. The ’LVTH18502A and ’LVTH182502A scan test devices with 18-bit universal bus transceivers are members of the Texas Instruments SCOPE™ testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface. Additionally, these devices are designed specifically for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. In the normal mode, these devices are 18-bit universal bus transceivers, that combine with D-type latches and D-type flip-flops, they allow data to flow in the transparent, latched, or clocked modes. Another use is as two 9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPE universal bus transceivers. Data flow in each direction is controlled by output-enable (OEAB\ and OEBA\), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A-bus data is latched while CLKAB is held at a static low or high logic level. Otherwise, if LEAB is low, A-bus data is stored on a low-to-high transition of CLKAB. When OEAB\ is low, the B outputs are active. When OEAB\ is high, the B outputs are in the high-impedance state. B-to-A data flow is similar to A-to-B data flow, but uses the OEBA\, LEBA, and CLKBA inputs. In the test mode, the normal operation of the SCOPE universal bus transceivers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990. Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudorandom pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The B-port outputs of ’LVTH182502A, which are designed to source or sink up to 12 mA, include 25-series resistors to reduce overshoot and undershoot. The SN54LVTH18502A and SN54LVTH182502A are characterized for operation over the full military temperature range of –55°C to 125°C. The SN74LVTH18502A and SN74LVTH182502A are characterized for operation from –40°C to 85°C.