Texas Instruments

These devices contain three independent 3-input NAND gates. They perform the Boolean functionsorin positive logic. The SN54F10 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F10 is characterized for operation from 0°C to 70°C. These devices contain three independent 3-input NAND gates. They perform the Boolean functionsorin positive logic. The SN54F10 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F10 is characterized for operation from 0°C to 70°C.

16-Bit Schottky Barrier Diode R-C Bus-Termination Array

This Schottky barrier diode bus-termination array is designed to reduce reflection noise on memory bus lines. This device consists of an 8-bit high-speed Schottky diode array suitable for a clamp to GND. The SN74F1056 is characterized for operation from 0°C to 70°C. This Schottky barrier diode bus-termination array is designed to reduce reflection noise on memory bus lines. This device consists of an 8-bit high-speed Schottky diode array suitable for a clamp to GND. The SN74F1056 is characterized for operation from 0°C to 70°C.

These devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset (PRE\) or clear (CLR\) inputs sets or resets the outputs regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K\ input meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K\ inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and trying J high. They also can perform as D-type flip-flops if J and K\ are tied together. The SN54F109 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F109 is characterized for operation from 0°C to 70°C. These devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset (PRE\) or clear (CLR\) inputs sets or resets the outputs regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K\ input meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K\ inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and trying J high. They also can perform as D-type flip-flops if J and K\ are tied together. The SN54F109 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F109 is characterized for operation from 0°C to 70°C.

These devices contain three independent 3-input AND gates. They perform the Boolean functionsorin positive logic. The SN54F11 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F11 is characterized for operation from 0°C to 70°C. These devices contain three independent 3-input AND gates. They perform the Boolean functionsorin positive logic. The SN54F11 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F11 is characterized for operation from 0°C to 70°C.

The SN74F112 contains two independent J-K negative-edge-triggered flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. Whenandare inactive (high), data at the J and K inputs meeting the setup time requirements is transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. The SN74F112 can perform as a toggle flip-flop by tying J and K high. The SN74F112 is characterized for operation from 0°C to 70°C. The SN74F112 contains two independent J-K negative-edge-triggered flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. Whenandare inactive (high), data at the J and K inputs meeting the setup time requirements is transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. The SN74F112 can perform as a toggle flip-flop by tying J and K high. The SN74F112 is characterized for operation from 0°C to 70°C.

The SN74F125 features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE)\ input is high. The SN74F125 features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE)\ input is high.

The ´F138 is designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible. The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. The SN54F138 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F138 is characterized for operation from 0°C to 70°C. The ´F138 is designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible. The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. The SN54F138 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F138 is characterized for operation from 0°C to 70°C.

These monolithic data selectors/multiplexers provide full binary decoding to select one of eight data sources. The strobe (G\) input must be at a low logic level to enable the data selection/multiplexing function. A high level at the strobe terminal forces the W output high and the Y output low. The SN54F151B is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F151B is characterized for operation from 0°C to 70°C. D0, D1,...D7 = the level of the respective D input. These monolithic data selectors/multiplexers provide full binary decoding to select one of eight data sources. The strobe (G\) input must be at a low logic level to enable the data selection/multiplexing function. A high level at the strobe terminal forces the W output high and the Y output low. The SN54F151B is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F151B is characterized for operation from 0°C to 70°C. D0, D1,...D7 = the level of the respective D input.

These data selectors/multiplexers contain inverters and drivers to supply full binary decoding data selection to the AND-OR gates. Separate strobe (G\) inputs are provided for each of the two 4-line sections. The SN54F153 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F153 is characterized for operation from 0°C to 70°C. These data selectors/multiplexers contain inverters and drivers to supply full binary decoding data selection to the AND-OR gates. Separate strobe (G\) inputs are provided for each of the two 4-line sections. The SN54F153 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F153 is characterized for operation from 0°C to 70°C.