SN65LVELT223.3-V dual LVTTL to differential LVPECL translator | Logic | 3 | Active | The SN65ELT22 is a dual LVTTL to differential LVPECL translator buffer. It operates on +3V supply and ground only. The output is driven default high when the inputs are left floating or unused. The low output skew makes the device the ideal solution for clock or data signal translation.
The SN65LVELT22 is housed in an industry standard SOIC-8 package and is also available in TSSOP-8 package option.
The SN65ELT22 is a dual LVTTL to differential LVPECL translator buffer. It operates on +3V supply and ground only. The output is driven default high when the inputs are left floating or unused. The low output skew makes the device the ideal solution for clock or data signal translation.
The SN65LVELT22 is housed in an industry standard SOIC-8 package and is also available in TSSOP-8 package option. |
SN65LVELT233.3-V dual differential LVPECL buffer to LVTTL translator | Logic | 2 | Active | The SN65LVELT23 is a low-power dual LVPECL/LVDS to LVTTL translator device. The device includes circuitry to maintain inputs at VCC/2 when left open. The SN65LVELT23 is housed in an industry-standard SOIC-8 package and is also available in a TSSOP-8 option.
The SN65LVELT23 is a low-power dual LVPECL/LVDS to LVTTL translator device. The device includes circuitry to maintain inputs at VCC/2 when left open. The SN65LVELT23 is housed in an industry-standard SOIC-8 package and is also available in a TSSOP-8 option. |
| Integrated Circuits (ICs) | 1 | Active | The SN65LVEP11 is a differential 1:2 PECL/ECL fanout buffer. The device includes circuitry to maintain known logic levels when the inputs are in an open condition. Single-ended clock input operation is limited to VCC≥ 3 V in PECL mode, or VEE≤ 3 V in NECL mode. The device is housed in an industry-standard SOIC-8 package and is also available in TSSOP-8 package option.
The SN65LVEP11 is a differential 1:2 PECL/ECL fanout buffer. The device includes circuitry to maintain known logic levels when the inputs are in an open condition. Single-ended clock input operation is limited to VCC≥ 3 V in PECL mode, or VEE≤ 3 V in NECL mode. The device is housed in an industry-standard SOIC-8 package and is also available in TSSOP-8 package option. |
SN65LVP162.5-V/3.3-V oscillator gain stage/buffer with enable | Interface | 1 | Active | These four devices are high-frequency oscillator gain stages supporting both LVPECL or LVDS on the high gain outputs in 3.3-V or 2.5-V systems. Additionally, provides the option of both single-ended input (PECL levels on the SN65LVx16) and fully differential inputs on the SN65LVx17.
The SN65LVx16 provides the user a Gain Control (GC) for controlling theQoutput from 300 mV to 860 mV either by leaving it open (NC), grounded, or tied to VCC. (When left open, theQoutput defaults to 575 mV.) TheQon the SN65LVx17 defaults to 575 mV as well.
Both devices provide a voltage reference (VBB) of typically 1.35 V below VCCfor use in receiving single-ended PECL input signals. When not used, VBBshould be unconnected or open.
All devices are characterized for operation from -40°C to 85°C.
These four devices are high-frequency oscillator gain stages supporting both LVPECL or LVDS on the high gain outputs in 3.3-V or 2.5-V systems. Additionally, provides the option of both single-ended input (PECL levels on the SN65LVx16) and fully differential inputs on the SN65LVx17.
The SN65LVx16 provides the user a Gain Control (GC) for controlling theQoutput from 300 mV to 860 mV either by leaving it open (NC), grounded, or tied to VCC. (When left open, theQoutput defaults to 575 mV.) TheQon the SN65LVx17 defaults to 575 mV as well.
Both devices provide a voltage reference (VBB) of typically 1.35 V below VCCfor use in receiving single-ended PECL input signals. When not used, VBBshould be unconnected or open.
All devices are characterized for operation from -40°C to 85°C. |
SN65LVP172.5-V/3.3-V oscillator gain stage/buffer with enable | Integrated Circuits (ICs) | 1 | Active | These four devices are high-frequency oscillator gain stages supporting both LVPECL or LVDS on the high gain outputs in 3.3-V or 2.5-V systems. Additionally, provides the option of both single-ended input (PECL levels on the SN65LVx16) and fully differential inputs on the SN65LVx17.
The SN65LVx16 provides the user a Gain Control (GC) for controlling theQoutput from 300 mV to 860 mV either by leaving it open (NC), grounded, or tied to VCC. (When left open, theQoutput defaults to 575 mV.) TheQon the SN65LVx17 defaults to 575 mV as well.
Both devices provide a voltage reference (VBB) of typically 1.35 V below VCCfor use in receiving single-ended PECL input signals. When not used, VBBshould be unconnected or open.
All devices are characterized for operation from -40°C to 85°C.
These four devices are high-frequency oscillator gain stages supporting both LVPECL or LVDS on the high gain outputs in 3.3-V or 2.5-V systems. Additionally, provides the option of both single-ended input (PECL levels on the SN65LVx16) and fully differential inputs on the SN65LVx17.
The SN65LVx16 provides the user a Gain Control (GC) for controlling theQoutput from 300 mV to 860 mV either by leaving it open (NC), grounded, or tied to VCC. (When left open, theQoutput defaults to 575 mV.) TheQon the SN65LVx17 defaults to 575 mV as well.
Both devices provide a voltage reference (VBB) of typically 1.35 V below VCCfor use in receiving single-ended PECL input signals. When not used, VBBshould be unconnected or open.
All devices are characterized for operation from -40°C to 85°C. |
SN65LVP182.5-V/3.3-V oscillator gain stage/buffer with enable | Interface | 1 | Active | These four devices are high frequency oscillator gain stages supporting both LVPECL or LVDS on the high gain outputs in 3.3-V or 2.5-V systems. Additionally, provides the option of both single-ended input (PECL levels on the SN65LVx18) and fully differential inputs on the SN65LVx19.
The SN65LVx18 provides the user a Gain Control (GC) for controlling theQoutput from 300 mV to 860 mV either by leaving it open (NC), grounded, or tied to VCC. (When left open, theQoutput defaults to 575 mV.) TheQon the SN65LVx19 defaults to 575 mV as well.
Both devices provide a voltage reference (VBB) of typically 1.35 V below VCCfor use in receiving single-ended PECL input signals. When not used, VBBshould be unconnected or open.
All devices are characterized for operation from -40°C to 85°C.
These four devices are high frequency oscillator gain stages supporting both LVPECL or LVDS on the high gain outputs in 3.3-V or 2.5-V systems. Additionally, provides the option of both single-ended input (PECL levels on the SN65LVx18) and fully differential inputs on the SN65LVx19.
The SN65LVx18 provides the user a Gain Control (GC) for controlling theQoutput from 300 mV to 860 mV either by leaving it open (NC), grounded, or tied to VCC. (When left open, theQoutput defaults to 575 mV.) TheQon the SN65LVx19 defaults to 575 mV as well.
Both devices provide a voltage reference (VBB) of typically 1.35 V below VCCfor use in receiving single-ended PECL input signals. When not used, VBBshould be unconnected or open.
All devices are characterized for operation from -40°C to 85°C. |
SN65LVP192.5-V/3.3-V oscillator gain stage/buffer with enable | Integrated Circuits (ICs) | 1 | Active | These four devices are high frequency oscillator gain stages supporting both LVPECL or LVDS on the high gain outputs in 3.3-V or 2.5-V systems. Additionally, provides the option of both single-ended input (PECL levels on the SN65LVx18) and fully differential inputs on the SN65LVx19.
The SN65LVx18 provides the user a Gain Control (GC) for controlling theQoutput from 300 mV to 860 mV either by leaving it open (NC), grounded, or tied to VCC. (When left open, theQoutput defaults to 575 mV.) TheQon the SN65LVx19 defaults to 575 mV as well.
Both devices provide a voltage reference (VBB) of typically 1.35 V below VCCfor use in receiving single-ended PECL input signals. When not used, VBBshould be unconnected or open.
All devices are characterized for operation from -40°C to 85°C.
These four devices are high frequency oscillator gain stages supporting both LVPECL or LVDS on the high gain outputs in 3.3-V or 2.5-V systems. Additionally, provides the option of both single-ended input (PECL levels on the SN65LVx18) and fully differential inputs on the SN65LVx19.
The SN65LVx18 provides the user a Gain Control (GC) for controlling theQoutput from 300 mV to 860 mV either by leaving it open (NC), grounded, or tied to VCC. (When left open, theQoutput defaults to 575 mV.) TheQon the SN65LVx19 defaults to 575 mV as well.
Both devices provide a voltage reference (VBB) of typically 1.35 V below VCCfor use in receiving single-ended PECL input signals. When not used, VBBshould be unconnected or open.
All devices are characterized for operation from -40°C to 85°C. |
| Integrated Circuits (ICs) | 2 | Active | The SN65LVDS20 and SN65LVP20 are a high-speed differential receiver and driver connected as a repeater. The receiver accepts low-voltage positive-emitter-coupled logic (PECL) at signaling rates up to 4 Gbps and repeats it as either an LVDS or PECL output signal. The signal path through the device is differential for low radiated emissions and minimal added jitter.
The outputs of the SN65LVDS20 are LVDS levels as defined by TIA/EIA-644-A. The outputs of the SN65LVDP20 are compatible with low-voltage PECL levels. A low-level input toENenables the outputs. A high-level input puts the output into a high-impedance state. Both outputs are designed to drive differential transmission lines with nominally 100-characteristic impedance.
Both devices provide a voltage reference (VBB) of typically 1.35 V below VCCfor use in receiving single-ended PECL input signals. When not used, VBBshould be unconnected or open.
All devices are characterized for operation from -40°C to 85°C.
The SN65LVDS20 and SN65LVP20 are a high-speed differential receiver and driver connected as a repeater. The receiver accepts low-voltage positive-emitter-coupled logic (PECL) at signaling rates up to 4 Gbps and repeats it as either an LVDS or PECL output signal. The signal path through the device is differential for low radiated emissions and minimal added jitter.
The outputs of the SN65LVDS20 are LVDS levels as defined by TIA/EIA-644-A. The outputs of the SN65LVDP20 are compatible with low-voltage PECL levels. A low-level input toENenables the outputs. A high-level input puts the output into a high-impedance state. Both outputs are designed to drive differential transmission lines with nominally 100-characteristic impedance.
Both devices provide a voltage reference (VBB) of typically 1.35 V below VCCfor use in receiving single-ended PECL input signals. When not used, VBBshould be unconnected or open.
All devices are characterized for operation from -40°C to 85°C. |
SN65LVPE501Dual channel single-lane PCI Express Gen II redriver | Signal Buffers, Repeaters, Splitters | 1 | Active | The SN65LVPE501 is a dual channel, single lane PCIe redriver and signal conditioner supporting data rates of up to 5.0Gbps. The device complies with PCIe spec revision 2.1.
Programmable EQ, De-Emphasis and Amplitude Swing
The SN65LVPE501 is designed to minimize the signal degradation effects such as crosstalk and inter-symbol interference (ISI) that limits the interconnect distance between two devices. The input stage of each channel offers selectable equalization settings that can be programmed to match loss in the channel. The differential outputs provide selectable de-emphasis to compensate for the anticipated distortion PCIe signal will experience. Level of de-emphasis will depend on the length of interconnect and its characteristics. Both equalization and de-emphasis levels are controlled by the setting of signal control pins EQ1, EQ2 and DE1, DE2.
To provide additional control of signal integrity in extended backplane applications LVPE501 provides independent output amplitude control for each channel. See for setting details.
Device PowerOnDevice initiates internal power-on reset after VCChas stabilized. External reset can also be applied at anytime by togglingRSTpin. External reset is recommended after every device power-up. WhenRSTis driven high, the device samples the state of EN_RXD, if it is set H device enters Rx.Detect state where each channel will perform Rx.Detect function (as described in PCIe spec). If EN_RXD is set L, automatic RX detect function is disabled and both channels are enabled with their termination set to ZDC_RX.
Receiver DetectionWhile EN_RXD pin is H and device is not in sleep mode (RSTis H), SN65LVPE501 performs RX.Detect on both channels indefinitely until remote termination is detected on both channels. Automatic Rx detection feature can be forced off by driving EN_RXD low. In this state both channels input termination are set to ZDC_RX.
Sleep (Shut_Down) ModeThis is low power state triggered byRST= L. In sleep mode receiver termination resistor for each of the two channels is switched to ZRX-HIGH_IMPof >50 KΩ and transmitters are pulled to Hi-Z state. Device power is reduced to <1mW (TYP). To get device out of sleep modeRSTis toggled L-H.
Electrical Idle SupportA link is in an electrical idle state when the TX± voltage is held at a steady constant value like the common mode voltage. SN65LVPE501 detects an electrical idle state when RX± input voltage of the associated channel falls below VEID_THmin. After detection of an electrical idle state in a given channel the device asserts electrical idle state in its corresponding TX. When RX± voltage exceeds VEID_THmax, normal device operation is restored and output starts passing input signal. Electrical idle exit and entry time is specified at ≤6ns.
Electrical idle support is independent for each channel.
Power Save FeaturesThe device supports three power save modes as described below.
1. Sleep (Shut_Down) Mode
This mode can be enabled from any state (Rx detect or active) by drivingRSTL. In this state both channels have their termination set to ZRX-HIGH_IMP+and outputs are at Hi-Z. Device power is 1mW (MAX)
2. Auto Low Power Mode
This mode is enabled when PS pin is tied H and device is in active mode. In this mode anytime Vindiff_ppfalls below selected VEID_THfor a and stays below VEID_THfor >1µs (TYP), the associated CH will enter auto low power (ALP) mode where power/CH will be reduced to <1/3rdof normal operating power/CH or about 70mW under typical voltage of 3.3V when ALP conditions are met for both channels. A CH will exit ALP mode whenever Vindiff_ppexceeds max VEID_THfor that channel. Exit latency is 30ns max. To use this mode link latency will need to account for the ALP exit time for N_FTS. ALP mode is handled by each channel independently based on its input differential signal level. This mode can be disabled by leaving PS as NC or tying PS to GND via 4.7kύ.
3. Cable Disconnect Mode
This mode is activated whenRSTis H, EN_RXD = H, and no termination is detected by either channel. Device is in the Rx.Detect state whereby it is continuously performing Rx.Detect on both channels. In this state total power consumed by device is typically <3% of normal active power. Or <10mW (MAX).
Beacon SupportWith its broadband design, the SN65LVPE501 supports low frequency Beacon signal (as defined by PCIe 2.1 spec) used to indicate wake-up event to the system by a downstream device when in L2 power state. All requirements for a beacon signal as specified in PCI Express specification 2.1 must be met for device to pass beacon signals.
Devic Power
The SN65LVPE501 is designed to operate from a single 3.3V supply. Always practice proper supply sequencing procedure. Apply VCCfirst before any input control pin signals are applied to the device. Power-down sequence is in reverse order.
The SN65LVPE501 is a dual channel, single lane PCIe redriver and signal conditioner supporting data rates of up to 5.0Gbps. The device complies with PCIe spec revision 2.1.
Programmable EQ, De-Emphasis and Amplitude Swing
The SN65LVPE501 is designed to minimize the signal degradation effects such as crosstalk and inter-symbol interference (ISI) that limits the interconnect distance between two devices. The input stage of each channel offers selectable equalization settings that can be programmed to match loss in the channel. The differential outputs provide selectable de-emphasis to compensate for the anticipated distortion PCIe signal will experience. Level of de-emphasis will depend on the length of interconnect and its characteristics. Both equalization and de-emphasis levels are controlled by the setting of signal control pins EQ1, EQ2 and DE1, DE2.
To provide additional control of signal integrity in extended backplane applications LVPE501 provides independent output amplitude control for each channel. See for setting details.
Device PowerOnDevice initiates internal power-on reset after VCChas stabilized. External reset can also be applied at anytime by togglingRSTpin. External reset is recommended after every device power-up. WhenRSTis driven high, the device samples the state of EN_RXD, if it is set H device enters Rx.Detect state where each channel will perform Rx.Detect function (as described in PCIe spec). If EN_RXD is set L, automatic RX detect function is disabled and both channels are enabled with their termination set to ZDC_RX.
Receiver DetectionWhile EN_RXD pin is H and device is not in sleep mode (RSTis H), SN65LVPE501 performs RX.Detect on both channels indefinitely until remote termination is detected on both channels. Automatic Rx detection feature can be forced off by driving EN_RXD low. In this state both channels input termination are set to ZDC_RX.
Sleep (Shut_Down) ModeThis is low power state triggered byRST= L. In sleep mode receiver termination resistor for each of the two channels is switched to ZRX-HIGH_IMPof >50 KΩ and transmitters are pulled to Hi-Z state. Device power is reduced to <1mW (TYP). To get device out of sleep modeRSTis toggled L-H.
Electrical Idle SupportA link is in an electrical idle state when the TX± voltage is held at a steady constant value like the common mode voltage. SN65LVPE501 detects an electrical idle state when RX± input voltage of the associated channel falls below VEID_THmin. After detection of an electrical idle state in a given channel the device asserts electrical idle state in its corresponding TX. When RX± voltage exceeds VEID_THmax, normal device operation is restored and output starts passing input signal. Electrical idle exit and entry time is specified at ≤6ns.
Electrical idle support is independent for each channel.
Power Save FeaturesThe device supports three power save modes as described below.
1. Sleep (Shut_Down) Mode
This mode can be enabled from any state (Rx detect or active) by drivingRSTL. In this state both channels have their termination set to ZRX-HIGH_IMP+and outputs are at Hi-Z. Device power is 1mW (MAX)
2. Auto Low Power Mode
This mode is enabled when PS pin is tied H and device is in active mode. In this mode anytime Vindiff_ppfalls below selected VEID_THfor a and stays below VEID_THfor >1µs (TYP), the associated CH will enter auto low power (ALP) mode where power/CH will be reduced to <1/3rdof normal operating power/CH or about 70mW under typical voltage of 3.3V when ALP conditions are met for both channels. A CH will exit ALP mode whenever Vindiff_ppexceeds max VEID_THfor that channel. Exit latency is 30ns max. To use this mode link latency will need to account for the ALP exit time for N_FTS. ALP mode is handled by each channel independently based on its input differential signal level. This mode can be disabled by leaving PS as NC or tying PS to GND via 4.7kύ.
3. Cable Disconnect Mode
This mode is activated whenRSTis H, EN_RXD = H, and no termination is detected by either channel. Device is in the Rx.Detect state whereby it is continuously performing Rx.Detect on both channels. In this state total power consumed by device is typically <3% of normal active power. Or <10mW (MAX).
Beacon SupportWith its broadband design, the SN65LVPE501 supports low frequency Beacon signal (as defined by PCIe 2.1 spec) used to indicate wake-up event to the system by a downstream device when in L2 power state. All requirements for a beacon signal as specified in PCI Express specification 2.1 must be met for device to pass beacon signals.
Devic Power
The SN65LVPE501 is designed to operate from a single 3.3V supply. Always practice proper supply sequencing procedure. Apply VCCfirst before any input control pin signals are applied to the device. Power-down sequence is in reverse order. |
SN65LVPE502CP1st generation dual channel USB 3.0 redriver with rotated package | Interface | 7 | NRND | The SN65LVPE502 is a dual channel, single lane USB 3.0 redriver and signal conditioner supporting data rates of 5.0Gbps. The device complies with USB 3.0 spec revision 1.0, supporting electrical idle condition and low frequency periodic signals (LFPS) for USB 3.0 power management modes.
Programmable EQ, De-Emphasis and Amplitude Swing
The SN65LVPE502 is designed to minimize signal degradation effects such as crosstalk and inter-symbol interference (ISI) that limits the interconnect distance between two devices. The input stage of each channel offers selectable equalization settings that can be programmed to match loss in the channel. The differential outputs provide selectable de-emphasis to compensate for the anticipated distortion USB 3.0 signal will experience. Level of de-emphasis will depend on the length of interconnect and its characteristics. The SN65LVPE502 provides a unique way to tailor output de-emphasis on a per channel basis with use of DE and OS pins. All Rx and Tx equalization settings supported by the device are programmed by six 3-state pins as shown in .
Low Power Modes
The device supports three low power modes as described below.
Initiated anytime EN_RXD undergoes a high to low transition or when device powers up with EN_RXD set low. In sleep mode both input and output terminations are held at HiZ and device ceases operation to conserve power. Sleep mode max power consumption is 1mW, entry time is 2µs, device exits sleep mode to Rx.Detect mode after EN_RXD is driven to VCC, exit time is 100µs max.
Anytime SN65LVPE502 detects a break in link (i.e., when upstream device is disconnected) or after powerup fails to find a remote device, SN65LVPE502 goes to Rx Detect mode and conserves power by shutting down majority of the internal circuitry. In this mode, input termination for both channels are driven to Hi-Z. In Rx Detect mode device power is <10mW(TYP) or less than 5% of its normal operating power This feature is useful in saving system power in mobile applications like notebook PC where battery life is critical.
Anytime an upstream device gets reconnected the redriver automatically senses the connection and goes to normal operating mode. This operation requires no setting to the device.
With the help of internal timers the device tracks when link enters USB 3.0 low power modes U2 and U3, in these modes link is in electrical idle state. SN65LVPE502 will selectively turn-off internal circuitry to save on power. Typical power saving is about 75% lower than normal operating mode. The device will automatically revert to active mode when signaling activity (LFPS) is detected.
Receiver Detection
RX.Detect cycle is performed by first setting Rx termination for each channel to Hi-Z, device then starts sensing for receiver termination that may be attached at the other end of each TX.
If receiver is detected on both channel:
If no receiver is detected on one or both channels:
USB Compliance Mode
The device enters USB compliance mode when both EN_RXD and CM pins are set H. This mode is used to test the transmitter for compliance to voltage and timing specifications per USB 3.0 compliance specs. In this mode each channel will maintain its low-impedance termination RDC-RX, while auto Rx detect operation in the device is disabled.
Electrical Idle Support
The electrical idle support is needed for low frequency periodic signaling (LFPS) used in USB 3.0 side band communication. A link is in an electrical idle state when the TX± voltage is held at a steady constant value like the common mode voltage. SN65LVPE502 detects an electrical idle state when RX± voltage at the device pin falls below VRX_IDLE_DIFFppmin. After detection of an idle state in a given channel the device asserts electrical idle state in its corresponding TX. When RX± voltage exceeds VRX_IDLE_DIFFppmax normal operation is restored and output start passing input signal. The electrical idle exit and entry time is specified at ≤6 ns.
The SN65LVPE502 is a dual channel, single lane USB 3.0 redriver and signal conditioner supporting data rates of 5.0Gbps. The device complies with USB 3.0 spec revision 1.0, supporting electrical idle condition and low frequency periodic signals (LFPS) for USB 3.0 power management modes.
Programmable EQ, De-Emphasis and Amplitude Swing
The SN65LVPE502 is designed to minimize signal degradation effects such as crosstalk and inter-symbol interference (ISI) that limits the interconnect distance between two devices. The input stage of each channel offers selectable equalization settings that can be programmed to match loss in the channel. The differential outputs provide selectable de-emphasis to compensate for the anticipated distortion USB 3.0 signal will experience. Level of de-emphasis will depend on the length of interconnect and its characteristics. The SN65LVPE502 provides a unique way to tailor output de-emphasis on a per channel basis with use of DE and OS pins. All Rx and Tx equalization settings supported by the device are programmed by six 3-state pins as shown in .
Low Power Modes
The device supports three low power modes as described below.
Initiated anytime EN_RXD undergoes a high to low transition or when device powers up with EN_RXD set low. In sleep mode both input and output terminations are held at HiZ and device ceases operation to conserve power. Sleep mode max power consumption is 1mW, entry time is 2µs, device exits sleep mode to Rx.Detect mode after EN_RXD is driven to VCC, exit time is 100µs max.
Anytime SN65LVPE502 detects a break in link (i.e., when upstream device is disconnected) or after powerup fails to find a remote device, SN65LVPE502 goes to Rx Detect mode and conserves power by shutting down majority of the internal circuitry. In this mode, input termination for both channels are driven to Hi-Z. In Rx Detect mode device power is <10mW(TYP) or less than 5% of its normal operating power This feature is useful in saving system power in mobile applications like notebook PC where battery life is critical.
Anytime an upstream device gets reconnected the redriver automatically senses the connection and goes to normal operating mode. This operation requires no setting to the device.
With the help of internal timers the device tracks when link enters USB 3.0 low power modes U2 and U3, in these modes link is in electrical idle state. SN65LVPE502 will selectively turn-off internal circuitry to save on power. Typical power saving is about 75% lower than normal operating mode. The device will automatically revert to active mode when signaling activity (LFPS) is detected.
Receiver Detection
RX.Detect cycle is performed by first setting Rx termination for each channel to Hi-Z, device then starts sensing for receiver termination that may be attached at the other end of each TX.
If receiver is detected on both channel:
If no receiver is detected on one or both channels:
USB Compliance Mode
The device enters USB compliance mode when both EN_RXD and CM pins are set H. This mode is used to test the transmitter for compliance to voltage and timing specifications per USB 3.0 compliance specs. In this mode each channel will maintain its low-impedance termination RDC-RX, while auto Rx detect operation in the device is disabled.
Electrical Idle Support
The electrical idle support is needed for low frequency periodic signaling (LFPS) used in USB 3.0 side band communication. A link is in an electrical idle state when the TX± voltage is held at a steady constant value like the common mode voltage. SN65LVPE502 detects an electrical idle state when RX± voltage at the device pin falls below VRX_IDLE_DIFFppmin. After detection of an idle state in a given channel the device asserts electrical idle state in its corresponding TX. When RX± voltage exceeds VRX_IDLE_DIFFppmax normal operation is restored and output start passing input signal. The electrical idle exit and entry time is specified at ≤6 ns. |
