STMicroelectronics

The M95512 devices are electrically erasable programmable memories (EEPROMs) organized as 65536 x 8 bits, accessed through the SPI bus. The M95512-W can operate with a supply voltage from 2.5 V to 5.5 V, the M95512-R can operate with a supply voltage from 1.8 V to 5.5 V and the M95512-DF can operate with a supply voltage from 1.7 V to 5.5 V, over an ambient temperature range of -40 °C / +85 °C. The M95512-DF offers an additional page, named the Identification page (128 bytes). The Identification page can be used to store sensitive application parameters that can be (later) permanently locked in read-only mode. The SPI bus signals are C, D and Q, as shown in Figure 1 and Table 1. The device is selected when Chip select (S) is driven low. Communications with the device can be interrupted when the HOLD is driven low.

The M95640-A125 and M95640-A145 are 64-Kbit serial EEPROM Automotive grade devices operating up to 145°C. They are compliant with the very high level of reliability defined by the Automotive standard AEC-Q100 grade 0. The devices are accessed by a simple serial SPI compatible interface running up to 20 MHz. The memory array is based on advanced true EEPROM technology (Electrically Erasable PROgrammable Memory). The M95640-A125 and M95640-A145 are byte-alterable memories (8192 × 8 bits) organized as 256 pages of 32 byte in which the data integrity is significantly improved with an embedded Error Correction Code logic. The M95640-A125 and M95640-A145 offer an additional Identification Page (32 byte) in which the ST device identification can be read. This page can also be used to store sensitive application parameters which can be later permanently locked in read-only mode.

The M95640-A125 and M95640-A145 are 64-Kbit serial EEPROM Automotive grade devices operating up to 145°C. They are compliant with the very high level of reliability defined by the Automotive standard AEC-Q100 grade 0. The devices are accessed by a simple serial SPI compatible interface running up to 20 MHz. The memory array is based on advanced true EEPROM technology (Electrically Erasable PROgrammable Memory). The M95640-A125 and M95640-A145 are byte-alterable memories (8192 × 8 bits) organized as 256 pages of 32 byte in which the data integrity is significantly improved with an embedded Error Correction Code logic. The M95640-A125 and M95640-A145 offer an additional Identification Page (32 byte) in which the ST device identification can be read. This page can also be used to store sensitive application parameters which can be later permanently locked in read-only mode.

The M95640 devices are electrically erasable programmable memories (EEPROMs) organized as 8192 x 8 bits, accessed through the SPI bus. The M95640-W can operate with a supply voltage from 2.5 V to 5.5 V, the M95640-R can operate with a supply voltage from 1.8 V to 5.5 V and the M95640-DF can operate with a supply voltage from 1.7 V to 5.5 V, over an ambient temperature range of -40 °C / +85 °C. The M95640-D offers an additional page, named the identification page (32 bytes). The identification page can be used to store sensitive application parameters which can be (later) permanently locked in read-only mode. The SPI bus signals are C, D and Q. The device is selected when chip select (S) is driven low. Communications with the device can be interrupted when the HOLD is driven low.

The M95640-DRE is a 64-Kbit serial EEPROM device operating up to 105 °C. The M95640-DRE is compliant with the level of reliability defined by the AEC-Q100 grade 2. The device is accessed by a simple serial SPI compatible interface running up to 20 MHz. The memory array is based on advanced true EEPROM technology (Electrically Erasable PROgrammable Memory). The M95640-DRE is a byte-alterable memory (8192 × 8 bits) organized as 256 pages of 32 bytes in which the data integrity is significantly improved with an embedded Error Correction Code logic. The M95640-DRE offers an additional Identification Page (32 bytes) in which the ST device identification can be read. This page can also be used to store sensitive application parameters which can be later permanently locked in read-only mode.

The M95640 devices are electrically erasable programmable memories (EEPROMs) organized as 8192 x 8 bits, accessed through the SPI bus. The M95640-W can operate with a supply voltage from 2.5 V to 5.5 V, the M95640-R can operate with a supply voltage from 1.8 V to 5.5 V and the M95640-DF can operate with a supply voltage from 1.7 V to 5.5 V, over an ambient temperature range of -40 °C / +85 °C. The M95640-D offers an additional page, named the identification page (32 bytes). The identification page can be used to store sensitive application parameters which can be (later) permanently locked in read-only mode. The SPI bus signals are C, D and Q. The device is selected when chip select (S) is driven low. Communications with the device can be interrupted when the HOLD is driven low.

The M95640 devices are electrically erasable programmable memories (EEPROMs) organized as 8192 x 8 bits, accessed through the SPI bus. The M95640-W can operate with a supply voltage from 2.5 V to 5.5 V, the M95640-R can operate with a supply voltage from 1.8 V to 5.5 V and the M95640-DF can operate with a supply voltage from 1.7 V to 5.5 V, over an ambient temperature range of -40 °C / +85 °C. The M95640-D offers an additional page, named the identification page (32 bytes). The identification page can be used to store sensitive application parameters which can be (later) permanently locked in read-only mode. The SPI bus signals are C, D and Q. The device is selected when chip select (S) is driven low. Communications with the device can be interrupted when the HOLD is driven low.

The M95M01-A125 and M95M01-A145 are 1-Mbit serial EEPROM Automotive grade devices operating up to 145°C. They are compliant with the very high level of reliability defined by the Automotive standard AEC-Q100 grade 0. The devices are accessed by a simple serial SPI compatible interface running up to 16 MHz. The memory array is based on advanced true EEPROM technology (Electrically Erasable PROgrammable Memory). The M95M01-A125 and M95M01-A145 are byte-alterable memories (131072 × 8 bits) organized as 512 pages of 256 bytes in which the data integrity is significantly improved with an embedded Error Correction Code logic. The M95M01-A125 and M95M01-A145 offer an additional Identification Page (256 bytes) in which the ST device identification can be read. This page can also be used to store sensitive application parameters which can be later permanently locked in read-only mode.

The M95M02-A125 is 2-Mbit serial EEPROM Automotive grade device operating up to 125°C. The M95M02-A125 is compliant with the very high level of reliability defined by the Automotive standard AEC-Q100 grade 0. The device is accessed by a simple serial SPI compatible interface running up to 10 MHz. The memory array is based on advanced true EEPROM technology (Electrically Erasable PROgrammable Memory). The M95M02-A125 is byte-alterable memories (262144 × 8 bits) organized as 1024 pages of 256 byte in which the data integrity is significantly improved with an embedded Error Correction Code logic. The M95M02-A125 offers an additional Identification Page (256 byte) in which the ST device identification can be read. This page can also be used to store sensitive application parameters which can be later permanently locked in read-only mode.

The M95M02 devices are electrically erasable programmable memory (EEPROM) organized as 262144 x 8 bits, accessed through the SPI bus. Over an ambient temperature range of -40 °C / +85 °C the M95M02-DR can operate with a supply voltage from 1.8 to 5.5 V. Over an ambient temperature range of -20 °C / +85 °C the M95M02-DF can operate with a supply voltage from 1.7 to 5.5 V. The M95M02 devices offer an additional page, named the Identification page (256 bytes). The Identification page can be used to store sensitive application parameters that can be (later) permanently locked in read-only mode. The SPI bus signals are C, D and Q, as shown in Figure 1 and Table 1. The device is selected when chip select (S) is driven low. Communications with the device can be interrupted when the HOLD is driven low.