Renesas Electronics Corporation

The 72845 is a 4K x 18 First-In, First-Out memory with clocked read and write controls. It is functionally equivalent to two 72245 FIFOs in a single package with all associated control, data, and flag lines assigned to independent pins and would be applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.

The 7285 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.

The 72851 is a 8K x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72251 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72851 architecture lends itself to many flexible configurations such as: 2-level priority data buffering, Bidirectional operation, Width expansion and Depth expansion.

A ST-BUS® compatible digital switch controlled by amicroprocessor which can handle from 128 x 128 to 32K x 32K inputs to multiple outputs.

The 728981 is an ST-BUS® compatible digital switch controlled by a microprocessor. The device can handle as many as 128, 64Kbit/s input and output channels. Those 128 channels are divided into four serial inputs and outputs, each of which consists of 32 channels (64Kbit/s per channel) to form a multiplexed 2.048Mb/s stream.

The 7290820 is a non-blocking digital switch that has a capacity of 2,048 x 2,048 channels at a serial bit rate of 8.192Mb/s, 1,024 x 1,024 channels at 4.096Mb/s, and 512 x 512 channels at 2.048Mb/s. Some of the main features include programmable stream and channel control, Processor mode, input offset delay, and high-impedance output control. Per-stream input delay control is provided for managing large multi-chip switches that transport both voice channels and concatenated data channels. In addition, input streams can be individually calibrated for input frame offset. The device is an ST-BUS®compatible digital switch controlled by a microprocessor that can handle from 128 x 128 to 32K x 32K inputs to multiple outputs.

The 72T18105 is a 128K x 18 / 256K x 9 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x18/x9 data flow. Bus-Matching TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.

The 72T18125 is a 512K x 18 / 1M x 9 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x18/x9 data flow. Bus-Matching TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.