Renesas Electronics Corporation

The 5V80001 is a high-performance clock interface for use in MOST® (Media Oriented Systems Transport) enabled systems. It can be used in two modes: generating a master clock for the ring, or performing clock/data recovery in a slave node.

The 5V925BI is a high-performance, low skew, low jitter phase-locked loop (PLL) clock driver. It provides precise phase and frequency alignment of its clock outputs to an externally applied clock input or internal crystal oscillator. The 5V925BI has been specially designed to interface with Gigabit Ethernet and Fast Ethernet applications by providing a 125MHz clock from 25MHz input. It can also be programmed to provide output frequencies ranging from 3.125MHz to 160MHz with input frequencies ranging from 3.125MHz to 80MHz.

The 5V9910A is a high fanout phase locked-loop clock driver intended for high performance computing and data-communications applications. It has eight zero delay LVTTL outputs. When the GND/sOE pin is held low, all the outputs are synchronously enabled. However, if GND/sOE is held high, all the outputs except Q2 and Q3 are synchronously disabled. Furthermore, when the VCCQ/PE is held high, all the outputs are synchronized with the positive edge of the REF clock input. When VCCQ/ PE is held low, all the outputs are synchronized with the negative edge of REF. The FB signal is compared with the input REF signal at the phase detector in order to drive the VCO. Phase differences cause the VCO of the PLL to adjust upwards or downwards accordingly. An internal loop filter moderates the response of the VCO to the phase detector. The loop filter transfer function has been chosen to provide minimal jitter (or frequency variation) while still providing accurate responses to input frequency changes.