Renesas Electronics Corporation

The MK2302-01 is a high-performance Zero Delay Buffer (ZDB) that integrates Renesas' proprietary analog/digital Phase-Locked Loop (PLL) techniques. The chip is part of Renesas' ClockBlocks™ family and was designed as a performance upgrade to meet today's higher speed and lower voltage requirements. The zero delay feature means that the rising edge of the input clock aligns with the rising edges of both output clocks, giving the appearance of no delay through the device. There are two outputs on the chip, one being a low-skew divide by two of the other output. The MK2302-01 is ideal for synchronizing outputs in a large variety of systems, from personal computers to data communications to graphics/video. By allowing off-chip feedback paths, the device can eliminate the delay through other devices.

The MK2304-1 is a low jitter, low skew, high performance Phase Lock Loop (PLL) based zero delay buffer for high speed applications. Based on IDT's proprietary low jitter PLL techniques, the device provides four low skew outputs at speeds up to 133 MHz at 3.3 V. The MK2304-1 includes two banks of two outputs each 1X. In the zero delay mode, the rising edge of the input clock is aligned with the rising edges of all 4 outputs. Compared to competitive CMOS devices, the MK2304-1 has the lowest jitter. IDT manufactures the largest variety of clock generators and buffers and is the largest clock supplier in the world.

The MK2304-2 is a low jitter, low skew, high performance Phase Lock Loop (PLL) based zero delay buffer for high speed applications. Based on IDT's proprietary low jitter PLL techniques, the device provides four low skew outputs at speeds up to 133 MHz at 3.3 V. The MK2304-2 includes a bank of two outputs running at 1/2X. In the zero delay mode, the rising edge of the input clock is aligned with the rising edges of all 4 outputs. Compared to competitive CMOS devices, the MK2304-2 has the lowest jitter. The MK2304-2 PLL enters a power-down state when there are no rising edges on the REF input. In this mode, all outputs are tri-stated and the PLL is turned off, resulting in leass than 25 ?A of current draw. IDT manufactures the largest variety of clock generators and buffers and is the largest clock supplier in the world.

The MK2308 is a low phase noise, high-speed PLL based, 8 output, low skew zero delay buffer. Based on IDT's proprietary low jitter Phase Locked Loop (PLL) techniques, the device provides eight low skew outputs at speeds up to 133 MHz at 3.3 V. The outputs can be generated from the PLL (for zero delay), or directly from the input (for testing), and can be set to tri-state mode or to stop at a low level. For normal operation as a zero delay buffer, any output clock is tied to the FBIN pin.

The MK2712 is the ideal way to generate clocks for NTSC/PAL video encoders and decoders. Stored in the device are two sets of popular frequencies for NTSC and PAL. In an 8 pin SOIC, the chip can save component count, board space, and cost over surface mount crystals and oscillators, and increase reliability by eliminating one or two mechanical devices from the board. The power down pin turns off the device, drawing less than 20?A. ICS/MicroClock offers many other clocks for computers and computer peripherals. Consult us when you need to remove crystals and oscillators from your board.

The MK2716 is a low-cost, low jitter, high-performance PLL clock synthesizer designed to produce the 74.176 MHz and 74.25 MHz clocks necessary for HDTV systems. Using IDT's patented analog Phase-Locked Loop (PLL) techniques, the device accepts a 27 MHz crystal or clock input. The zero ppm synthesis error exactly locks the display to the digital stream. IDT manufactures the largest variety multimedia clock synthesizers for all applications. Consult IDT to eliminate crystals and oscillators from your board. For applications that require lower jitter, such as SDI and pixel clocks, use the 664.