Renesas Electronics Corporation

The MK1581-01 provides synchronization and timing control for T1 and E1 based network access or multitrunk telecommunication systems. The device accepts an 8 kHz frame clock input and uses an on-chip VCXO to produce a synchronized low phase noise clock output. This monolithic IC, combined with an external inexpensive quartz crystal, can be used to replace a more costly hybrid VCXO retiming module. Through selection of external loop filter components values, the device can be tailored to meet the system's clock jitter attenuation requirements. Low-pass jitter attenuation characteristics in the Hz range are possible.

The MK1709 generates a low EMI output clock from a clock input. The part is designed to dither the LCD interface clock for flat panel graphics controllers. The device uses IDT's proprietary mix of analog and digital Phase Locked Loop (PLL) technology to spread the frequency spectrum of the output, thereby reducing the frequency amplitude peaks by several dB. The MK1709 offers centered spread from a high speed clock input. Refer to the MK1714-01/02 for a crystal input and the widest selection of input frequencies and multipliers. IDT offers many other clocks for computers and computer peripherals. Consult us when you need to remove crystals and oscillators from your board.

The MK1714-01 is a low cost, high performance clock synthesizer with selectable multipliers and percentages of spread spectrum designed to generate high frequency clocks with low EMI. Using analog/digital Phase Locked Loop (PLL) techniques, the device accepts an inexpensive, fundamental mode, parallel resonant crystal or clock input to produce a spread or dithered output. This reduces the EMI amplitude peaks at the odd harmonics by several dB. The OE pin places both outputs into a high impedance state for board level testing. The PD pin powers down the entire chip and the outputs are held low. See the MK1714-02 for other selections on input ranges and spreads.

The MK1728A-01 generates a low EMI output clock from a clock or crystal input. Operating at 2.5 V, the part is designed to dither the LCD interface clock for PDAs, printers, scanners, modems, copiers, and other applications. Using IDT's proprietary mix of analog and digital Phase-Locked Loop (PLL) technology, the device spreads the frequency spectrum of the output, reducing the frequency amplitude peaks by several dB. The MK1728A-01 offers both centered and down spread from a high-speed crystal or clock input. IDT offers many other clocks for computers and computer peripherals. Consult IDT when you need to remove crystals and oscillators from your board.

The MK2049-45 is a dual Phase-Locked Loop (PLL) device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate input jitter. The second PLL is a translator for frequency multiplication. Basic configuration is determined by a Mode/Frequency Selection Table. Loop bandwidth and damping factor are programmable via external loop filter component selection. Buffer Mode accepts a 10 to 50MHz input and will provide a jitter attenuated output at 0.5 x ICLK, 1 x ICLK or 2 x ICLK. In this mode the MK2049-45 is ideal for filtering jitter from high frequency clocks. In External Mode, ICLK accepts an 8 kHz clock and will produce output frequencies from a table of common communications clock rates, CLK and CLK/2. This allows for the generation of clocks frequency-locked to an 8 kHz backplane clock, simplifying clock synchronization in communications systems. The MK2049-45 can be dynamically switched between T1, E1, T3, E3 outputs with the same 24.576 MHz crystal. ICS can customize these devices for many other different frequencies. Contact your ICS representative for more details.

The MK2058-01 is a VCXO (Voltage Controlled Crystal Oscillator) based clock jitter attenuator designed for system clock distribution applications. This monolithic IC, combined with an external inexpensive quartz crystal, can be used to replace a more costly hybrid VCXO retiming module. The device accepts and outputs the same clock frequency in selectable ranges covering 4 kHz to 27 MHz. A dual input mux is also provided. By controlling the VCXO frequency within a phase-locked loop (PLL), the output clock is phase and frequency locked to the input clock. Through selection of external loop filter components, the PLL loop bandwidth and damping factor can be tailored to meet system clock requirements. A loop bandwidth down to the Hz range is possible.

The MK2069-01 is a VCXO (Voltage Controlled Crystal Oscillator) based clock generator that offers system synchronization, jitter attenuation, and frequency multiplication or translation. It can accept an unstable, jittery input clock and provide a de-jittered, low phase noise output clock at a user determined frequency. The device's clock multiplication ratios are user selectable since all major PLL divider blocks can be configured through device pin settings. External PLL loop filter components allow tailoring of the VCXO PLL loop response and therefore the clock jitter attenuation characteristics. The MK2069-01 is ideal for line card applications. Its three input MUX enables selection of the master or slave (backup) system clocks, as well as a backup local line card clock. The lock detector (LD) output serves as a clock status monitor. The clear (CLR) input enables rapid synchronization to the phase of a newly selected input clock, while eliminating the generation of extra clock cycles and wander caused by memory in the PLL feedback divider. CLR also serves as a temporary holdover function when kept low.