Renesas Electronics Corporation

The 527-01 Clock Slicer is the most flexible way to generate an output clock from an input clock with zero skew. The user can easily configure the device to produce nearly any output clock that is multiplied or divided from the input clock. The part supports non-integer multiplications and divisions. A SYNC pulse indicates when the rising clock edges are aligned with zero skew. Using Phase-Locked Loop (PLL) techniques, the device accepts an input clock up to 200 MHz and produces an output clock up to 160 MHz. The 527-01 aligns rising edges on ICLK and FBIN at a ratio determined by the reference and feedback dividers. For configurable clocks that do not require zero delay, use the 525.

The 542 is cost effective way to produce a high-quality clock output divided from a clock input. The chip accepts a clock input up to 156 MHz at 3.3 V and produces a divide by 2, 4, 6, 8, 12, or 16 of the input clock. There are two outputs on the chip, one being a low-skew divide by two of the other. For instance, if an 100 MHz input clock is used, the 542 can produce low-skew 50 MHz and 25 MHz clocks, or low skew 25 MHz and 12.5 MHz clocks. The chip has an all-chip power-down mode that stops the outputs low, and an OE pin that tri-states the outputs. See the 501, 502, 511, 512, and 525 for clock multipliers.

The 548-05 is a low-cost, low-jitter, high-performance clock synthesizer designed to produce x16 and x24 clocks from T1 and E1 frequencies. Using Renesas’ patented analog/digital Phase-Locked Loop (PLL) techniques, the device uses a crystal or clock input to synthesize popular communications frequencies. Power down modes allow the chip to turn off completely, or the PLL and clock output to be turned off separately.

The 548-05 is a low-cost, low-jitter, high-performance clock synthesizer designed to produce x16 and x24 clocks from T1 and E1 frequencies. Using Renesas’ patented analog/digital Phase-Locked Loop (PLL) techniques, the device uses a crystal or clock input to synthesize popular communications frequencies. Power down modes allow the chip to turn off completely, or the PLL and clock output to be turned off separately.

The 54FCT162244T 16-bit high-speed and low-power buffer/line driver is for bus interface or signal buffering applications and has three-state controls allowing independent 4-bit, 8-bit, or combined 16-bit operation. The 54FCT162244T operates at -55 °C to +125 °C. For the commercial version, see 74FCT162244T.

The 54FCT162245T 16-bit high-speed, low-power transceiver is ideal for synchronous communication between two buses and can operate as either two independent 8-bit transceivers or one 16-bit transceiver. The 54FCT162245T operates at -55 °C to +125 °C. For the commercial version, see 74FCT162245T.

The 54FCT16245T 16-bit high-speed, low-power transceiver is ideal for synchronous communication between two buses. The Direction and Output Enable controls operate these devices as either two independent 8-bit transceivers or one 16-bit transceiver. The 54FCT16245T operates at -55C to +125C. (For commercial version, see 74FCT16245T)