Renesas Electronics Corporation

The 8T49N285 has one fractional-feedback PLL that can be used as a frequency translator with jitter attenuation or a frequency synthesizer. It is equipped with six integer and two fractional output dividers, allowing the generation of up to eight different output frequencies, ranging from 8 kHz to 1 GHz. Output frequencies can be completely independent of the input frequencies, and up to three of these frequencies can be completely independent of each other. The eight outputs may select among LVPECL, LVDS, HCSL or LVCMOS output levels. The 8T49N285 is ideal for use in a wide range of equipment, including 10G/40G/100G SONET/SDH and Ethernet network line cards, wireless base station baseband units, broadcast video, carrier Ethernet switches, OTN, or in test and measurement applications. For example, the 8T49N285 can be used in GbE/10GbE/100GbE Synchronous Ethernet line card applications in order to preserve the G.8262 compliance from the Synchronous Equipment Timing Source (SETS) on the timing card. Renesas’ third generation Universal Frequency Translator family also includes the8T49N286(4-in / 2-PLL / 8-out), and8T49N287(2-in / 2-PLL / 8-out), and the8T49N242(2-in / 1-PLL / 4-out). These devices are complemented by the82P33714and82P33731synchronous equipment timing source (SETS) for Synchronous Ethernet (SyncE) and 10G-40G SyncE, respectively. To see other devices in this product family, visit theUniversal Frequency Translatorspage.

The 8T49N4811 is a highly flexible FemtoClock®NG pin-programmable clock generator suitable for networking and communications applications. It can generate five different output frequencies with multiple copies of each. A fundamental mode crystal, single-ended, or differential input reference may be used as the source for the output frequency. The use of pin programming to select the input source/frequency, desired output frequencies, and output styles allows a single device to be used in a wide variety of applications without the need for register programming. Selection pins use 3-level options to maximize flexibility while minimizing package size. Selection is performed by tying a selection pin high or low or by leaving it floating, eliminating the need for passive components to drive a desired logic level.