MC100EPT622 Series

Translator, 10-bit LVTTL / LVCMOS to LVPECL

Catalog

Translator, 10-bit LVTTL / LVCMOS to LVPECL

Part	Translator Type	Number of Circuits	Channel Type	Operating Temperature [Max]	Operating Temperature [Min]	Package / Case	Output Type	Channels per Circuit	Mounting Type	Supplier Device Package	Input Signal	Output Signal
ON Semiconductor MC100EPT622MNR4G	Mixed Signal	1	Unidirectional	85 °C	-40 °C	32-VFQFN Exposed Pad	Non-Inverted	10	Surface Mount	32-QFN (5x5)	LVCMOS LVTTL	LVPECL
ON Semiconductor MC100EPT622FA	Mixed Signal	1	Unidirectional	85 °C	-40 °C	32-LQFP	Non-Inverted	10	Surface Mount	32-LQFP (7x7)	LVCMOS LVTTL	LVPECL
ON Semiconductor MC100EPT622MNG	Mixed Signal	1	Unidirectional	85 °C	-40 °C	32-VFQFN Exposed Pad	Non-Inverted	10	Surface Mount	32-QFN (5x5)	LVCMOS LVTTL	LVPECL
ON Semiconductor MC100EPT622FAG	Mixed Signal	1	Unidirectional	85 °C	-40 °C	32-LQFP	Non-Inverted	10	Surface Mount	32-LQFP (7x7)	LVCMOS LVTTL	LVPECL
ON Semiconductor MC100EPT622FAR2	Mixed Signal	1	Unidirectional	85 °C	-40 °C	32-LQFP	Non-Inverted	10	Surface Mount	32-LQFP (7x7)	LVCMOS LVTTL	LVPECL

Catalog

Translator, 10-bit LVTTL / LVCMOS to LVPECL

Key Features

• 450 ps Typical Propogation Delay

• Maximum Frequency > 1.5 GHz Typical

• PECL Mode

• Operating Range: VCC= 3.0 V to 3.8 V with VEE= 0 V

• PNP LVTTL Inputs for Minimal Loading

• Q Outputs Will Default HIGH with Inputs Open

• The 100 Series Contains Temperature Compensation

Description

The MC100EPT622 is a 10-Bit LVTTL/LVCMOS to LVPECL translator. Because LVPECL (Positive ECL) levels are used, only +3.3 V and ground are required. The device has an OR-ed enable input which can accept either LVPECL (ENPECL) or TTL/LVCMOS inputs (ENTTL). If the inputs are left open, they will default to the enable state. The device design has been optimized for low channel-to-channel skew.