| Logic | 1 | Active | The 74ALVCH16600 is an 18-bit universal transceiver with bus hold inputs and 3-state outputs. Data flow in each direction is controlled by output enable (OEABandOEBA), latch enable (LEAB and LEBA), clock enable (CEABandCEBA) and clock (CPABandCPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CPAB is held at a HIGH or LOW logic level. If LEAB andCEABare LOW, the A-bus data is stored in the latch/flip-flop on the HIGH-to-LOW transition ofCPAB. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in the high-impedance state. |
| Integrated Circuits (ICs) | 1 | Obsolete | |
| Universal Bus Functions | 1 | Active | The 74ALVCH16601 is an 18-bit universal transceiver with bus hold inputs and 3-state outputs. Data flow in each direction is controlled by output enable (OEABandOEBA), latch enable (LEAB and LEBA), clock enable (CEABandCEBA) and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CPAB is held at a HIGH or LOW logic level. If LEAB andCEABare LOW, the A-bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CPAB. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in the high-impedance state. Data flow for B-to-A is similar to that of A-to-B but usesOEBA, LEBA,CEBAand CPBA. This device is fully specified for partial power down applications using IOFF. The IOFFcircuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. |
| Buffers, Drivers, Receivers, Transceivers | 2 | Obsolete | |
| Integrated Circuits (ICs) | 1 | Active | The 74ALVCH16646 consists of 16 non-inverting bus transceiver circuits with 3-state outputs, D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the internal registers. Data on the ‘A’ or ‘B’ bus will be clocked in the internal registers, as the appropriate clock (nCPAB or nCPBA) goes to a HIGH logic level. Output enable (nOE) and direction (nDIR) inputs are provided to control the transceiver function. In the transceiver mode, data present at the high-impedance port may be stored in either the ‘A’ or ‘B’ register, or in both. The select source inputs (nSAB and nSBA) can multiplex stored and real-time (transparent mode) data. The direction (nDIR) input determines which bus will receive data when nOEis active (LOW). In the isolation mode (nOE= HIGH), ‘A’ data may be stored in the ‘B’ register and/or ‘B’ data may be stored in the ‘A’ register. |
| Buffers, Drivers, Receivers, Transceivers | 1 | Obsolete | The 74ALVCH16652 consists of 16 non-inverting bus transceiver circuits with 3-state outputs, D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. |
74ALVCH16821DGG20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state | Flip Flops | 1 | Obsolete | The 74ALVCH16821 has two 10-bit, edge triggered registers, with each register coupled to a 3-state output buffer. The two sections of each register are controlled independently by the clock (nCP) and output enable nOEcontrol gates. |
74ALVCH16823DGG18-bit bus-interface D-type flip-flop with reset and enable; 3-state | Logic | 1 | Obsolete | The 74ALVCH16823 is an 18-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. Incorporates bushold data inputs which eliminate the need for external pull-up resistors to hold unused inputs. The 74ALVCH16823 consists of two sections of nine edge-triggered flip-flops. A clock (nCP) input, an output-enable (nOE) input, a master reset (nMR) input and a clock-enable (nCE) input are provided for each total 9-bit section. |
| Buffers, Drivers, Receivers, Transceivers | 3 | Obsolete | |
| Buffers, Drivers, Receivers, Transceivers | 1 | Active | The 74ALVCH16825 is an 18–bit non-inverting buffer/driver with 3-state outputs for bus-oriented applications. The 74ALVCH16825 consists of two 9-bit sections with separate output enable signals. For either 9-bit buffer section, the two output enable (1OE1and 1OE2or 2OE1and 2OE2) inputs must both be LOW for corresponding nYn outputs to be active. If either output enable input is HIGH, the outputs of that 9-buffer section are in the high impedance state. |
