Nexperia USA Inc.

The 74ALVCH16827 is a 20-bit non-inverting buffer/driver with 3-state outputs for bus oriented applications.

The 74ALVCH16843 has two 9–bit D-type latch featuring separate D-type inputs for each latch and 3-State outputs for bus oriented applications. The two sections of each register are controlled independently by the latch enable (nLE), clear (nCLR), preset (nPRE) and output enable (nOE) control gates.

The 74ALVCH16952 consists of two sections, each containing a dual octal non-inverting registered transceiver. Two 8-bit back to back registers store data flowing in both directions between two bidirectional buses. Data applied to the inputs is entered and stored on the rising edge of the clock (nCPAB and nCPBA) provided that the clock enable (nCEABand nCEBA) is LOW. The data is then present at the output buffers, but is only accessible when the output enable input (nOEABand nOEBA) is LOW. Data flow from A inputs to B outputs is the same as for B inputs to A outputs.

The 74ALVT16244 is a 16-bit buffer/line driver with 3-state outputs. The device can be used as four 4-bit buffers, two 8-bit buffers or one 16-bit buffer. The device features four output enables (1OE, 2OE, 3OEand 4OE), each controlling four of the 3-state outputs. A HIGH on nOEcauses the outputs to assume a high-impedance OFF-state. Bus hold data inputs eliminate the need for external pull-up resistors to define unused inputs