74ALVC74DDual D-type flip-flop with set and reset; positive-edge trigger | Integrated Circuits (ICs) | 1 | Active | The 74ALVC74 is a dual positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q andQoutputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. |
74ALVC74PWDual D-type flip-flop with set and reset; positive-edge trigger | Logic | 1 | Active | The 74ALVC74 is a dual positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q andQoutputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. |
74ALVC74PW-Q100Dual D-type flip-flop with set and reset; positive-edge trigger | Flip Flops | 1 | Active | The 74ALVC74-Q100 is a dual positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q andQoutputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. |
| Buffers, Drivers, Receivers, Transceivers | 2 | Obsolete | |
74ALVCH162244DGG16-bit buffer/line driver with 30 Ω termination resistor; 3-state | Integrated Circuits (ICs) | 1 | Active | The 74ALVCH162244 is a 16-bit buffer/line driver with bus hold inputs, 30 Ω termination resistors and 3-state outputs. The device can be used as four 4-bit buffers, two 8-bit buffers or one 16-bit buffer. The device features four output enables (1OE, 2OE, 3OEand 4OE), each controlling four of the 3-state outputs. A HIGH on nOEcauses the outputs to assume a high-impedance OFF-state. This device is fully specified for partial power down applications using IOFF. The IOFFcircuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. |
| Buffers, Drivers, Receivers, Transceivers | 4 | Active | |
74ALVCH162442.5 V / 3.3 V 16-bit buffer/line driver; 3-state | Buffers, Drivers, Receivers, Transceivers | 5 | Active | The 74ALVC16244; 74ALVCH16244 is a 16-bit buffer/line driver with 3-state outputs. The device can be used as four 4-bit buffers, two 8-bit buffers or one 16-bit buffer. The device features four output enables (1OE,2OE,3OEand4OE), each controlling four of the 3-state outputs. A HIGH onnOEcauses the outputs to assume a high-impedance OFF-state. |
| Integrated Circuits (ICs) | 1 | Active | The 74ALVC16245; 74ALVCH16245 is a 16-bit transceiver with 3-state outputs. The device can be used as two 8-bit transceivers or one 16-bit transceiver. The device features two output enables (1OE and 2OE) each controlling eight outputs, and two send/receive (1DIR and 2DIR) inputs for direction control. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. |
| Logic | 3 | Obsolete | |
74ALVCH162601DGG18-bit universal bus transceiver with 30 Ohm termination resistor; 3-state | Integrated Circuits (ICs) | 1 | Active | The 74ALVCH162601 is an 18-bit universal transceiver with bus hold inputs, 30 Ω termination resistors and 3-state outputs. Data flow in each direction is controlled by output enable (OEABandOEBA), latch enable (LEAB and LEBA), clock enable (CEABandCEBA) and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CPAB is held at a HIGH or LOW logic level. If LEAB andCEABare LOW, the A-bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CPAB. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in the high-impedance state. Data flow for B-to-A is similar to that of A-to-B but usesOEBA, LEBA,CEBAand CPBA.. This device is fully specified for partial power down applications using IOFF. The IOFFcircuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. |
