74ALVC374Octal D-type flip-flop; positive-edge trigger; 3-state | Flip Flops | 5 | Active | The 74ALVC374 is an octal positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH onOEcauses the outputs to assume a high-impedance OFF-state. Operation of theOEinput does not affect the state of the flip-flops. |
| Integrated Circuits (ICs) | 4 | Active | The 74ALVC541-Q100 is an 8-bit buffer/line driver with 3-state outputs. The device features two output enables (OE1 andOE2). A HIGH onOEn causes the associated outputs to assume a high-impedance OFF-state. |
| Integrated Circuits (ICs) | 1 | Active | The 74ALVC541 is an 8-bit buffer/line driver with 3-state outputs. The device features two output enables (OE1 andOE2). A HIGH onOEn causes the associated outputs to assume a high-impedance OFF-state. |
| Integrated Circuits (ICs) | 1 | Active | The 74ALVC541 is an 8-bit buffer/line driver with 3-state outputs. The device features two output enables (OE1 andOE2). A HIGH onOEn causes the associated outputs to assume a high-impedance OFF-state. |
74ALVC573Octal D-type transparent latch; 3-state | Integrated Circuits (ICs) | 3 | Active | The 74ALVC573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH onOEcauses the outputs to assume a high-impedance OFF-state. Operation of theOEinput does not affect the state of the latches. |
| Logic | 1 | Active | The 74ALVC573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH onOEcauses the outputs to assume a high-impedance OFF-state. Operation of theOEinput does not affect the state of the latches. |
74ALVC574Octal D-type flip-flop; positive edge-trigger; 3-state | Flip Flops | 3 | Active | The 74ALVC574 is an 8-bit positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH onOEcauses the outputs to assume a high-impedance OFF-state. Operation of theOEinput does not affect the state of the flip-flops. |
74ALVC574BQOctal D-type flip-flop; positive edge-trigger; 3-state | Integrated Circuits (ICs) | 1 | Active | The 74ALVC574 is an 8-bit positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH onOEcauses the outputs to assume a high-impedance OFF-state. Operation of theOEinput does not affect the state of the flip-flops. |
| Integrated Circuits (ICs) | 1 | Active | |
74ALVC74BQDual D-type flip-flop with set and reset; positive-edge trigger | Integrated Circuits (ICs) | 1 | Active | The 74ALVC74 is a dual positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q andQoutputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. |
