74ALVCH162601DGG Series

The 74ALVCH162601 is an 18-bit universal transceiver with bus hold inputs, 30 Ω termination resistors and 3-state outputs. Data flow in each direction is controlled by output enable (OEABandOEBA), latch enable (LEAB and LEBA), clock enable (CEABandCEBA) and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CPAB is held at a HIGH or LOW logic level. If LEAB andCEABare LOW, the A-bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CPAB. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in the high-impedance state. Data flow for B-to-A is similar to that of A-to-B but usesOEBA, LEBA,CEBAand CPBA.. This device is fully specified for partial power down applications using IOFF. The IOFFcircuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.