74LV1658-bit parallel-in/serial-out shift register | Integrated Circuits (ICs) | 2 | Active | The 74LV165 is an 8-bit serial or parallel-in/serial-out shift register. The device features a serial data input (DS), eight parallel data inputs (D0 to D7) and two complementary serial outputs (Q7 andQ7). When the parallel load input (PL) is LOW the data from D0 to D7 is loaded into the shift register asynchronously. WhenPLis HIGH data enters the register serially at DS. When the clock enable input (CE) is LOW data is shifted on the LOW-to-HIGH transitions of the CP input. A HIGH onCEwill disable the CP input. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess VCC. |
74LV165AD8-bit parallel-in/serial-out shift register | Shift Registers | 1 | Active | The 74LV165A is an 8-bit parallel-load or serial-in shift register with complementary serial outputs (Q7 andQ7) available from the last stage. When the parallel-load input (PL) is LOW, parallel data from the inputs D0 to D7 are loaded into the register asynchronously. When inputPLis HIGH, data enters the register serially at the input DS. It shifts one place to the right (Q0 → Q1 → Q2, etc.) with each positive-going clock transition. This feature allows parallel-to-serial converter expansion by tying the output Q7 to the input DS of the succeeding stage. |
| Shift Registers | 1 | Active | The 74LV165A-Q100 is an 8-bit parallel-load or serial-in shift register with complementary serial outputs (Q7 andQ7) available from the last stage. When the parallel-load input (PL) is LOW, parallel data from the inputs D0 to D7 are loaded into the register asynchronously. When inputPLis HIGH, data enters the register serially at the input DS. It shifts one place to the right (Q0 → Q1 → Q2, etc.) with each positive-going clock transition. This feature allows parallel-to-serial converter expansion by tying the output Q7 to the input DS of the succeeding stage. The clock input is a gate-OR structure which allows one input to be used as an active LOW clock enable input (CE) input. The pin assignment for the inputs CP andCEis arbitrary and can be reversed for layout convenience. The LOW-to-HIGH transition of the inputCEshould only take place while CP HIGH for predictable operation. |
74LV165APW8-bit parallel-in/serial-out shift register | Integrated Circuits (ICs) | 1 | Active | The 74LV165A is an 8-bit parallel-load or serial-in shift register with complementary serial outputs (Q7 andQ7) available from the last stage. When the parallel-load input (PL) is LOW, parallel data from the inputs D0 to D7 are loaded into the register asynchronously. When inputPLis HIGH, data enters the register serially at the input DS. It shifts one place to the right (Q0 → Q1 → Q2, etc.) with each positive-going clock transition. This feature allows parallel-to-serial converter expansion by tying the output Q7 to the input DS of the succeeding stage. |
| Integrated Circuits (ICs) | 1 | Active | The 74LV165A-Q100 is an 8-bit parallel-load or serial-in shift register with complementary serial outputs (Q7 andQ7) available from the last stage. When the parallel-load input (PL) is LOW, parallel data from the inputs D0 to D7 are loaded into the register asynchronously. When inputPLis HIGH, data enters the register serially at the input DS. It shifts one place to the right (Q0 → Q1 → Q2, etc.) with each positive-going clock transition. This feature allows parallel-to-serial converter expansion by tying the output Q7 to the input DS of the succeeding stage. The clock input is a gate-OR structure which allows one input to be used as an active LOW clock enable input (CE) input. The pin assignment for the inputs CP andCEis arbitrary and can be reversed for layout convenience. The LOW-to-HIGH transition of the inputCEshould only take place while CP HIGH for predictable operation. |
74LV165D8-bit parallel-in/serial-out shift register | Integrated Circuits (ICs) | 1 | Active | The 74LV165 is an 8-bit serial or parallel-in/serial-out shift register. The device features a serial data input (DS), eight parallel data inputs (D0 to D7) and two complementary serial outputs (Q7 andQ7). When the parallel load input (PL) is LOW the data from D0 to D7 is loaded into the shift register asynchronously. WhenPLis HIGH data enters the register serially at DS. When the clock enable input (CE) is LOW data is shifted on the LOW-to-HIGH transitions of the CP input. A HIGH onCEwill disable the CP input. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess VCC. |
| Shift Registers | 1 | Active | The 74LV165-Q100 is an 8-bit serial or parallel-in/serial-out shift register. The device features a serial data input (DS), eight parallel data inputs (D0 to D7) and two complementary serial outputs (Q7 andQ7). When the parallel load input (PL) is LOW the data from D0 to D7 is loaded into the shift register asynchronously. WhenPLis HIGH data enters the register serially at DS. When the clock enable input (CE) is LOW data is shifted on the LOW-to-HIGH transitions of the CP input. A HIGH onCEwill disable the CP input. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess VCC. |
| Logic | 1 | Active | The 74LV165-Q100 is an 8-bit serial or parallel-in/serial-out shift register. The device features a serial data input (DS), eight parallel data inputs (D0 to D7) and two complementary serial outputs (Q7 andQ7). When the parallel load input (PL) is LOW the data from D0 to D7 is loaded into the shift register asynchronously. WhenPLis HIGH data enters the register serially at DS. When the clock enable input (CE) is LOW data is shifted on the LOW-to-HIGH transitions of the CP input. A HIGH onCEwill disable the CP input. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess VCC. |
| Integrated Circuits (ICs) | 1 | Active | The 74LV17A is a hex buffer with Schmitt-trigger inputs, capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. |
74LV1T002-input single supply translating NAND gate | Gates and Inverters | 2 | Active | The 74LV1T00 is a single, level translating 2-input NAND gate. The low threshold inputs support 1.8 V input logic at VCC= 3.3 V and can be used in 1.8 V to 3.3 V level up translation. In addition, the 5 V tolerant input pins enable level down translation (3.3 V to 2.5 V output at VCC= 2.5 V). The output level is referenced to the supply voltage and supports 1.8 V, 2.5 V, 3.3 V and 5.0 V CMOS levels. The wide VCCrange permits the generation of output levels to connect to controllers or processors. |
