74LV165PW-Q100 Series

The 74LV165-Q100 is an 8-bit serial or parallel-in/serial-out shift register. The device features a serial data input (DS), eight parallel data inputs (D0 to D7) and two complementary serial outputs (Q7 andQ7). When the parallel load input (PL) is LOW the data from D0 to D7 is loaded into the shift register asynchronously. WhenPLis HIGH data enters the register serially at DS. When the clock enable input (CE) is LOW data is shifted on the LOW-to-HIGH transitions of the CP input. A HIGH onCEwill disable the CP input. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess VCC.