| Gates and Inverters | 1 | Active | The 74LV132-Q100 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC132-Q100 and 74HCT132-Q100. |
| Integrated Circuits (ICs) | 4 | Active | |
| Signal Switches, Multiplexers, Decoders | 1 | Active | The 74LV138-Q100 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 toY7). The 74LV138-Q100 features three enable inputs (Y1,Y2 and E3). Every output will be HIGH unlessY1 andY2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion of the 74LV138-Q100 to a 1-of-32 (5 to 32 lines) decoder with just four 74LV138 ICs and one inverter. The 74LV138-Q100 can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess VCC. |
74LV14Hex inverting Schmitt trigger | Logic | 6 | Active | The 74LV14 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC14 and 74HCT14. |
| Gates and Inverters | 1 | Active | The 74LV14A is a hex inverter with Schmitt-trigger inputs, capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. |
| Logic | 1 | Active | The 74LV14 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC14 and 74HCT14. |
| Logic | 1 | Active | The 74LV14-Q100 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC14-Q100 and 74HCT14-Q100. |
| Gates and Inverters | 1 | Active | The 74LV14-Q100 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC14-Q100 and 74HCT14-Q100. |
74LV1648-bit serial-in/parallel-out shift register | Shift Registers | 5 | Active | The 74LV164 is an 8-bit serial-in/parallel-out shift register. The device features two serial data inputs (DSA and DSB), eight parallel outputs (Q0 to Q7). Data is entered serially through DSA or DSB and either input can be used as an active HIGH enable for data entry through the other input. Data is shifted on the LOW-to-HIGH transition of the clock input (CP). A LOW on the master reset input (MR) clears the register and forces all outputs LOW, independently of other inputs. |
74LV164D8-bit serial-in/parallel-out shift register | Logic | 1 | Active | The 74LV164 is an 8-bit serial-in/parallel-out shift register. The device features two serial data inputs (DSA and DSB), eight parallel outputs (Q0 to Q7). Data is entered serially through DSA or DSB and either input can be used as an active HIGH enable for data entry through the other input. Data is shifted on the LOW-to-HIGH transition of the clock input (CP). A LOW on the master reset input (MR) clears the register and forces all outputs LOW, independently of other inputs. |
