74LV165APW-Q100 Series

The 74LV165A-Q100 is an 8-bit parallel-load or serial-in shift register with complementary serial outputs (Q7 andQ7) available from the last stage. When the parallel-load input (PL) is LOW, parallel data from the inputs D0 to D7 are loaded into the register asynchronously. When inputPLis HIGH, data enters the register serially at the input DS. It shifts one place to the right (Q0 → Q1 → Q2, etc.) with each positive-going clock transition. This feature allows parallel-to-serial converter expansion by tying the output Q7 to the input DS of the succeeding stage. The clock input is a gate-OR structure which allows one input to be used as an active LOW clock enable input (CE) input. The pin assignment for the inputs CP andCEis arbitrary and can be reversed for layout convenience. The LOW-to-HIGH transition of the inputCEshould only take place while CP HIGH for predictable operation.