Microchip Technology

The MEC1322 incorporates a high-performance 32-bit embedded microcontroller with 128 Kilobytes of SRAM and 32 Kilobytes of Boot ROM which communicates with the system host using the Intel® Low Pin Count (LPC) bus. The product has two Serial Peripheral Interface (SPI) memory interfaces that allow the Embedded Controller (EC) to read its code from external SPI flash memory: private SPI and/or shared SPI. The Shared SPI interface allows for Embedded Controller code to be stored in a shared SPI chip along with the system BIOS. It provides support for loading EC code from the private or shared SPI flash device on a VCC1 power-on. The MEC1322 is directly powered by two separates suspend supply planes (VBAT and VCC1) and senses the runtime power plane (VCC) to provide "Instant On" and system power management functions. **Family parts**MEC1322I-NU-C0 MEC1322-LZY MEC1322-LZY-C0 MEC1322-LZY-C0-TR MEC1322-NU MEC1322-NU-C0 MEC1322-SZ-C0 MEC1322-SZ-C0-TR

The MEC140X/1X family is a highly-configurable, mixed signal, advanced I/O controller architecture. MEC1406 is a keyboard and embedded controller customized for notebooks and tablet platforms. It incorporates a 32-bit MIPS32 M14K Microcontroller core with 160KB of closely-coupled SRAM for code and data that loads from SPI Flash. Designers can leverage the host SPI-flash (used for BIOS storage) for non-volatile EC firmware storage, as a cost-effective system solution. Microchip’s MEC14XX family reduces the system bill-of-materials cost by providing a flexible arrangement that allows multiple I/O signals to be configured to support either 3.3V or 1.8V. This eliminates the need for external voltage translators. The MEC1406 communicates with the system host through Intel Low Pin Count (LPC) or I2C. All members of the MEC14XX family are pin and register compatible and are supported by Microchip’s development tools. Examples include the MPLAB® XC Compilers, the MPLAB REAL ICE™In-Circuit Emulator (part # DV244005), the MPLAB ICD 3 In-Circuit Debugger (part # DV164035) and the PICkit™ 3 Starter Kit (part # DV164130). **Family parts**MEC1406-NU MEC1406-NU-D0

MEC1428 is the latest member of the MEC14XX family and adds a new level of design functionality for computing engineers by adding Slave Attached Flash (SAF), which is an optimal solution for USB Type-C™ power delivery. This device is pin and register compatible with the MEC140X and MEC141X families, which allows designers to easily add eSPI and additional features and have more flexibility in their designs. It retains eSPI Master Attached Flash (MAF) capability. The MEC14xx family is a keyboard and embedded controller customized for notebooks and computing platforms. The MEC140X/1X/2X family is a highly-configurable, mixed signal, advanced I/O controller architecture. MEC1428 incorporates a 32-bit MIPS32 M14K Microcontroller core with 192 KB of closely-coupled SRAM for code and data that loads from SPI Flash. Designers can leverage the host SPI-flash (used for BIOS storage) for non-volatile EC firmware storage, as a cost-effective system solution. Microchip’s MEC14XX family also provides a flexible arrangement that allows multiple I/O signals to be configured to support either 3.3V or 1.8V, reducing the system bill-of-materials cost by eliminating the need for external voltage translators. The MEC1428 communicates with the system host through the Intel Enhanced Serial Peripheral Interface (eSPI) or through Intel's Low Pin Count (LPC). All members of the MEC14XX family are pin and register compatible and are supported by Microchip’s development tools. Examples include the MPLAB® XC Compilers, the MPLAB REAL ICE™ In-Circuit Emulator (part # DV244005), the MPLAB ICD 3 In-Circuit Debugger (part # DV164035) and the PICkit™ 3 Starter Kit (part # DV164130). Additional products with eSPI capability: MEC1418, MEC1701, MEC1704, MEC1705 **Family parts**MEC1428-I/NU-C1 MEC1428-NU-C1 MEC1428-SZ-C1 MEC1428-SZ-C1-TR MEC1428-TF-C1 MEC1428-TF-C1-TR

The MEC152x is a family of low power integrated embedded controllers designed for notebook applications. The MEC152x is a highly-configurable, mixed-signal, advanced I/O controller architecture. It contains a 32-bit ARM® CortexM4 processor core with closely-coupled memory for optimal code execution and data access. An internal ROM, embedded in the design, is used to store the power on/boot sequence and APIs available during run time. When VTR\_CORE is applied to the device, the secure boot loader API is used to download the custom firmware image from the system’s shared SPI Flash device, thereby allowing system designers to customize the device’s behavior. The MEC152x device is directly powered by a minimum of two separate suspend supply planes (VBAT and VTR) and senses a third runtime power plane (VCC) to provide "instant on" and system power management functions. The MEC152x has two banks of I/O pins that are able to operate at either 3.3 V or 1.8 V. Operating at 1.8V allows the MEC152x to interface with the latest platform controller hubs and will lower the overall power consumed by the device, whereas 3.3V allows this device to be integrated into legacy platforms that require 3.3V operation. The MEC152x host interface is the Intel® Enhanced Serial Peripheral Interface (eSPI). The eSPI Interface is a 1.8V interface that operates in single, double and quad I/O modes. The eSPI Interface supports all four eSPI channels: Peripheral Channel, Virtual Wires Channel, OOB Message Channel, and Run-time Flash Access Channel. The eSPI hardware Flash Access Channel is used by the Boot ROM to support Master Attached Flash Sharing (MAFS). In addition, the MEC152x has specially designed hardware to support Slave Attached Flash Sharing (SAFS). The eSPI SAFS Bridge imposes Region-Based Protection and Locking security feature, which limits access to certain regions of the flash to specific masters. There may be one or more masters (e.g., BIOS, ME, etc) that will access the SAF via the eSPI interface. The ARM® Cortex-M4 processor is also considered a master, which will also have its access limited to EC only regions of SPI Flash as determined by the customer firmware application. The MEC152x secure boot loader authenticates and optionally decrypts the SPI Flash OEM boot image using the AES256, ECDSA , SHA-384 cryptographic hardware accelerators. The MEC152x hardware accelerators support 128-bit and 256-bit AES encryption, ECDSA and EC\_KCDSA signing algorithms, 1024-bits to 4096-bits RSA and Elliptic asymmetric public key algorithms, and a True Random Number Generator (TRNG). Runtime APIs are provided in the ROM for customer application code to use the cryptographic hardware. Additionally, the device offers lockable OTP storage for private keys and IDs. The MEC152x is designed to be incorporated into low power PC architecture designs and supports ACPI sleep states (S0-S5). During normal operation, the hardware always operates in the lowest power state for a given configuration. The chip power management logic offers two low power states: light sleep and heavy sleep. These features can be used to support S0 Connected Standby state and the lower ACPI S3-S5 system sleep states. In connected standby, any eSPI command will wake the device and be processed. When the chip is sleeping, it has many wake events that can be configured to return the device to normal operation. Some examples of supported wake events are PS2 wake events, RTC, Week Alarm, Hibernation Timer, or any GPIO pin. The MEC152x offers a software development system interface that includes a Trace FIFO Debug port, a host accessible serial debug port with a 16C550A register interface, a Port 80 BIOS Debug Port, and a 2-pin Serial Wire Debug (SWD) interface. Also included is a 4-wire JTAG interface used for Boundary Scan testing.

The MEC152x is a family of low power integrated embedded controllers designed for notebook applications. The MEC152x is a highly-configurable, mixed-signal, advanced I/O controller architecture. It contains a 32-bit ARM® CortexM4 processor core with closely-coupled memory for optimal code execution and data access. An internal ROM, embedded in the design, is used to store the power on/boot sequence and APIs available during run time. When VTR\_CORE is applied to the device, the secure boot loader API is used to download the custom firmware image from the system’s shared SPI Flash device, thereby allowing system designers to customize the device’s behavior. The MEC152x device is directly powered by a minimum of two separate suspend supply planes (VBAT and VTR) and senses a third runtime power plane (VCC) to provide "instant on" and system power management functions. The MEC152x has two banks of I/O pins that are able to operate at either 3.3 V or 1.8 V. Operating at 1.8V allows the MEC152x to interface with the latest platform controller hubs and will lower the overall power consumed by the device, whereas 3.3V allows this device to be integrated into legacy platforms that require 3.3V operation. The MEC152x host interface is the Intel® Enhanced Serial Peripheral Interface (eSPI). The eSPI Interface is a 1.8V interface that operates in single, double and quad I/O modes. The eSPI Interface supports all four eSPI channels: Peripheral Channel, Virtual Wires Channel, OOB Message Channel, and Run-time Flash Access Channel. The eSPI hardware Flash Access Channel is used by the Boot ROM to support Master Attached Flash Sharing (MAFS). In addition, the MEC152x has specially designed hardware to support Slave Attached Flash Sharing (SAFS). The eSPI SAFS Bridge imposes Region-Based Protection and Locking security feature, which limits access to certain regions of the flash to specific masters. There may be one or more masters (e.g., BIOS, ME, etc) that will access the SAF via the eSPI interface. The ARM® Cortex-M4 processor is also considered a master, which will also have its access limited to EC only regions of SPI Flash as determined by the customer firmware application. The MEC152x secure boot loader authenticates and optionally decrypts the SPI Flash OEM boot image using the AES256, ECDSA , SHA-384 cryptographic hardware accelerators. The MEC152x hardware accelerators support 128-bit and 256-bit AES encryption, ECDSA and EC\_KCDSA signing algorithms, 1024-bits to 4096-bits RSA and Elliptic asymmetric public key algorithms, and a True Random Number Generator (TRNG). Runtime APIs are provided in the ROM for customer application code to use the cryptographic hardware. Additionally, the device offers lockable OTP storage for private keys and IDs. The MEC152x is designed to be incorporated into low power PC architecture designs and supports ACPI sleep states (S0-S5). During normal operation, the hardware always operates in the lowest power state for a given configuration. The chip power management logic offers two low power states: light sleep and heavy sleep. These features can be used to support S0 Connected Standby state and the lower ACPI S3-S5 system sleep states. In connected standby, any eSPI command will wake the device and be processed. When the chip is sleeping, it has many wake events that can be configured to return the device to normal operation. Some examples of supported wake events are PS2 wake events, RTC, Week Alarm, Hibernation Timer, or any GPIO pin. The MEC152x offers a software development system interface that includes a Trace FIFO Debug port, a host accessible serial debug port with a 16C550A register interface, a Port 80 BIOS Debug Port, and a 2-pin Serial Wire Debug (SWD) interface. Also included is a 4-wire JTAG interface used for Boundary Scan testing.

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