Microchip Technology

MD1811 is a high speed, quad MOSFET driver designed to drive high voltage P and N-channel MOSFETs for medical ultrasound applications and other applications requiring a high output current for a capacitive load. The high-speed input stage of the MD1811 can operate from a 1.8 to 5.0V logic interface with an optimum operating input signal range of 1.8 to 3.3V. An adaptive threshold circuit is used to set the level translator switch threshold to the average of the input logic 0 and logic 1 levels. The input logic levels may be ground referenced, even though the driver is putting out bipolar signals. The level translator uses a proprietary circuit, which provides DC coupling together with high-speed operation. The output stage of the MD1811 has separate power connections enabling the output signal L and H levels to be chosen independently from the supply voltages used for the majority of the circuit. As an example, the input logic levels may be 0 and 1.8V, the control logic may be powered by +5.0 and -5.0V, and the output L and H levels may be varied anywhere over the range of -5.0 to +5.0V. The output stage is capable of peak currents of up to ±2.0A, depending on the supply voltages used and load capacitance present. The OE pin serves a dual purpose. First, its logic H level is used to compute the threshold voltage level for the channel input level translators. Secondly, when OE is low, the outputs are disabled, with the A & C output high and the B & D output low. This assists in properly pre-charging the AC coupling capacitors that may be used in series in the gate drive circuit of an external PMOS and NMOS transistor pair.

MD1812 is a high-speed quad MOSFET driver. It is designed to drive two N and two P-channel high voltage DMOS FETs for medical ultrasound applications, but may be used in any application that needs a high output current for a capacitive load. The input stage of the MD1812 is a high-speed level translator that is able to operate from logic input signals of 1.8 to 5.0V amplitude. An adaptive threshold circuit is used to set the level translator threshold to the average of the input logic 0 and logic 1 levels. The level translator uses a proprietary circuit which provides DC coupling together with high-speed operation. The output stage of the MD1812 has separate power connections enabling the output signal L and H levels to be chosen independently from the driver supply voltages. As an example, the input logic levels may be 0V and 1.8V, the control logic may be powered by +5V and –5V, and the output L and H levels may be varied anywhere over the range of -5.0 to +5.0V. The output stage is capable of peak currents of up to ±2.0 amps depending on the supply voltages used and load capacitance. The OE pin serves a dual purpose. First, its logic H level is used to compute the threshold voltage level for the channel input level translators. Secondly, when OE is low, the outputs are disabled, with the A and C outputs high and the B and D outputs low. This assists in properly pre-charging the coupling capacitors that may be used in series in the gate drive circuit of an external PMOS and NMOS. A built-in level shifter provides PMOS gate negative bias drive. This enables the user-defined damping control to generate return-to-zero bipolar output pulses.

MD1820 is a high speed, four channel MOSFET driver designed to drive high voltage P- and N-channel MOSFETs for medical ultrasound applications and other applications requiring a high output current for a capacitive load. The high-speed input stage of the MD1820 can operate from a 1.8 to 5.0V logic interface with an optimum operating input signal range of 1.8 to 3.3V. An adaptive threshold circuit is used to set the level translator switch threshold to the average of the input logic 0 and logic 1 levels. The input logic levels may be ground-referenced, even though the driver is putting out bipolar signals. The level translator uses a proprietary circuit, which provides DC coupling together with high-speed operation. The output stage of the MD1820 has separate power connections enabling the output signal L and H levels to be chosen independently from the supply voltages used for the majority of the circuit. As an example, the input logic levels may be 0 and 1.8V, the control logic may be powered by +5.0 and -5.0V, and the output L and H levels may be varied anywhere over the range of -5.0 to +5.0V. The output stage is capable of peak currents of up to ±2.0A, depending on the supply voltages used and load capacitance present. The PE pin serves a dual purpose. First, its logic H level is used to compute the threshold voltage level for the channel input level translators. Second, when PE is low, the outputs are HiZ. This assists in properly precharging the AC coupling capacitors that may be used in series in the gate drive circuit of an external PMOS and NMOS transistor pair.

MD1822 is a high speed, four channel MOSFET driver designed to drive high voltage P- and N-channel MOSFETs for medical ultrasound applications and other applications requiring a high output current for a capacitive load. The high-speed input stage of the MD1822 can operate from a 1.8 to 5.0V logic interface with an optimum operating input signal range of 1.8 to 3.3V. An adaptive threshold circuit is used to set the level translator switch threshold to the average of the input logic 0 and logic 1 levels. The input logic levels may be ground referenced, even though the driver is putting out bipolar signals. The level translator uses a proprietary circuit, which provides DC coupling together with high-speed operation. The output stage of the MD1822 has separate power connections enabling the output signal L and H levels to be chosen independently from the supply voltages used for the majority of the circuit. As an example, the input logic levels may be 0 and 1.8V, the control logic may be powered by +5.0 and -5.0V, and the output L and H levels may be varied anywhere over the range of -5.0 to +5.0V. The output stage is capable of peak currents of up to ±2.0A, depending on the supply voltages used and load capacitance present. The PE pin serves a dual purpose. First, its logic H level is used to compute the threshold voltage level for the channel input level translators. Second, when PE is low, the outputs are disabled, with the A & C output high and the B & D output low. This assists in properly precharging the AC coupling capacitors that may be used in series in the gate drive circuit of an external PMOS and NMOS transistor pair.

The MDA series of 3000 W Transient Voltage Suppressors (TVSs) protects a variety of voltage-sensitive components from destruction or degradation. They can protect from secondary lightning effects per IEC61000-4-5 and class levels defined herein, or for inductive switching environments and induced RF protection. Since their response time is virtually instantaneous, they can also be used in protection from ESD and EFT per IEC61000-4-2 and IEC61000-4-44

The MDA series of 3000 W Transient Voltage Suppressors (TVSs) protects a variety of voltage-sensitive components from destruction or degradation. They can protect from secondary lightning effects per IEC61000-4-5 and class levels defined herein, or for inductive switching environments and induced RF protection. Since their response time is virtually instantaneous, they can also be used in protection from ESD and EFT per IEC61000-4-2 and IEC61000-4-37

The MDA series of 3000 W Transient Voltage Suppressors (TVSs) protects a variety of voltage-sensitive components from destruction or degradation. They can protect from secondary lightning effects per IEC61000-4-5 and class levels defined herein, or for inductive switching environments and induced RF protection. Since their response time is virtually instantaneous, they can also be used in protection from ESD and EFT per IEC61000-4-2 and IEC61000-4-48

MEC1310 is a Notebook I/O Controller which incorporates a high-performance 8051- based keyboard and system controller with internal embedded 64KB SRAM, 1Kbyte Boot ROM, and 64- bytes battery backed registers. The embedded 64KB SRAM is loaded via HOST/8051 SPI (Serial Peripheral Interface) Memory Interface. The HOST/8051 SPI Memory Interface can be configured in Switched SPI Flash Configuration or Parallel Shared SPI Flash Configuration. It has two separate power planes to provide "instant on" and system power management functions. Additionally, the MEC1310 incorporates sophisticated power control circuitry (PCC). The PCC supports multiple low power down modes. **Family parts**MEC1310-NU MEC1310-NU-TR MEC1310-PZV