Microchip Technology

The CENTAUR KS8695X, Multi-Port Gateway-on-a-Chip, delivers a high level of networking integration and performance for accelerating broadband gateway development. Key components integrated in the KS8695X include: Integrated Layer 2 managed switch with five Fast Ethernet transceivers and patented mixed-signal low power technology, five media access control (MAC) units, a high-speed non-blocking switch fabric, a dedicated address look-up engine, an on-chip frame buffer memory, and LED controls. One port is partitioned for WAN interface with the other four ports for LAN access. Also integrated is a 166MHz ARM™ (ARM992T) processor with memory management unit (MMU) and 8KB I-cache and 8KB dCache. Shared programmable 8/16/32-bit data bus and 22-bit address bus with up to 64MB total memory space for SDRAM, ROM, Flash, SRAM, and all peripheral devices. Other peripheral support logic including GPIO, a watchdog timer, an interrupt controller, and a JTAG debugging interface. Complete hardware and software reference designs are available. The KS8695X represents a total solution optimized for broadband gateway system development and renders speedy routing performance and connectivity interfaces for value-added networking expansions. Microchip's complimentary and confidential [MicroCHECK](https://www.microchip.com/en-us/support/design-help/design-check-services) design review service, which offers insight from the initial concept to the final PCB layout, is available to customers who are using our products in their projects. You can confidently submit your design materials in a secure and private setting, and our expert engineers will provide individualized feedback to enhance your design. MicroCHECK design review service is subject to Microchip's [Program Terms and Conditions](https://www.microchip.com/en-us/support/design-help/design-check-services/design-check-services-program-terms-and-conditions) and requires a myMicrochip account.

The KSZ8765 is a highly integrated, Layer 2-managed, five-port switch with numerous features designed to reduce overall system cost. It is intended for cost-sensitive applications requiring four 10/100Mbps copper ports and one 10/100/1000Mbps Gigabit uplink port. The KSZ8765CLX incorporates a small package outline, low power consumption with internal biasing, and on-chip termination. Its extensive set of features include enhanced power management, programmable rate limiting and priority ratio, tagged and port-based VLAN, port-based security and ACL rule-based packet filtering technology, QoS priority with four queues, management interfaces, enhanced MIB counters, high-performance memory bandwidth, and a shared memory-based switch fabric with non-blocking support. The KSZ8765CLX provides support for multiple CPU data interfaces to effectively address both current and emerging fast Ethernet and Gigabit Ethernet applications where the Port 5 GMAC can be configured to any of the GMII, RGMII, MII, and RMII modes. The KSZ8765CLX is built upon Microchip's industry-leading Ethernet analog and digital technology, with features designed to offload host processing and streamline the overall design. • Two integrated MAC/PHYs 100Base-FX on Port 1 and Port 2 • Two integrated MAC/PHYs 10/100Base-T/TX on Port 3 and Port 4 • One integrated 10/100/1000Base-T/TX GMAC with selectable GMII, RGMII, MII, and RMII interfaces • Small 80-pin LQFP package A robust assortment of power management features including energy-efficient Ethernet (EEE), power management event (PME), and wake-on-LAN (WoL) have been designed in to satisfy energy efficient environments. All registers in the MAC/PHY units can be managed through the SPI interface. MIIM PHY registers can be accessed through the MDC/MDIO interface. Microchip's complimentary and confidential [MicroCHECK](https://www.microchip.com/en-us/support/design-help/design-check-services) design review service, which offers insight from the initial concept to the final PCB layout, is available to customers who are using our products in their projects. You can confidently submit your design materials in a secure and private setting, and our expert engineers will provide individualized feedback to enhance your design. MicroCHECK design review service is subject to Microchip's [Program Terms and Conditions](https://www.microchip.com/en-us/support/design-help/design-check-services/design-check-services-program-terms-and-conditions) and requires a myMicrochip account.

The KSZ8775CLX is a highly integrated, Layer 2-managed, five-port switch with numerous features designed to reduce system cost. It is intended for cost-sensitive applications requiring three 10/100Mbps copper ports, one RMII on Port 4, and one 10/100/1000Mbps Gigabit uplink port on Port 5. The KSZ8775CLX incorporates a small package outline, the lowest power consumption with internal biasing, and on-chip termination. Its extensive set of features include enhanced power management, programmable rate limiting and priority ratio, tagged and port-based VLAN, port-based security and ACL rule-based packet filtering technology, QoS priority with four queues, management interfaces, enhanced MIB counters, high-performance memory bandwidth, and a shared memory-based switch fabric with non-blocking support. The KSZ8775CLX provides support for multiple CPU data interfaces to effectively address both current and emerging fast Ethernet and Gigabit Ethernet applications where the Port 5 GMAC can be configured to any of the RGMII, MII, and RMII modes. The KSZ8775CLX product is built upon Microchip's industry-leading Ethernet analog and digital technology, with features designed to offload host processing and streamline the overall design. • Three integrated 10/100Base-T/TX MAC/PHYs • One integrated 10/100Base-T/TX MAC with RMII interface • One integrated 10/100/1000Base-T/TX GMAC with selectable RGMII, MII, and RMII interfaces • Small 80-pin LQFP package A robust assortment of power management features including energy-efficient Ethernet (EEE), power management event (PME), and wake-on-LAN (WoL) have been designed in to satisfy energy efficient environments. All registers in the MAC/PHY units can be managed through the SPI interface. MIIM PHY registers can be accessed through the MDC/MDIO interface. Microchip's complimentary and confidential [MicroCHECK](https://www.microchip.com/en-us/support/design-help/design-check-services) design review service, which offers insight from the initial concept to the final PCB layout, is available to customers who are using our products in their projects. You can confidently submit your design materials in a secure and private setting, and our expert engineers will provide individualized feedback to enhance your design. MicroCHECK design review service is subject to Microchip's [Program Terms and Conditions](https://www.microchip.com/en-us/support/design-help/design-check-services/design-check-services-program-terms-and-conditions) and requires a myMicrochip account.

The KSZ8794CNX is a highly integrated, Layer 2 managed, four-port switch with numerous features designed to reduce system cost. It is intended for cost-sensitive applications requiring three 10/100Mbps copper ports and one 10/100/1000Mbps Gigabit uplink port. The KSZ8794CNX incorporates a small package outline, low power consumption with internal biasing, and on-chip termination. Its extensive features set includes enhanced power management, programmable rate limiting and priority ratio, tagged and port-based VLAN, port-based security and ACL rule-based packet filtering technology, QoS priority with four queues, management interfaces, enhanced MIB counters, high-performance memory bandwidth, and a shared memory-based switch fabric with non-blocking support. The KSZ8794CNX provides support for multiple CPU data interfaces to effectively address both current and emerging fast Ethernet and Gigabit Ethernet applications where the GMAC interface can be configured to any of RGMII, MII and RMII modes. The KSZ8794CNX is built on Microchip's latest industry-leading Ethernet analog and digital technology, with features designed to offload host processing and streamline your overall design: • Three integrated 10/100Base-T/TX MAC/PHYs • One integrated 10/100/1000Base-T/TX GMAC with selectable RGMII, MII or RMII interfaces • Small 64-pin QFN package A robust assortment of power management features including Energy Efficient Ethernet (EEE), PME and WoL have been designed in to satisfy energy efficient environments. All registers in the MAC and PHY units can be managed through the SPI interface. MIIM PHY registers can be accessed through the MDC/MDIO interface. Microchip's complimentary and confidential [MicroCHECK](https://www.microchip.com/en-us/support/design-help/design-check-services) design review service, which offers insight from the initial concept to the final PCB layout, is available to customers who are using our products in their projects. You can confidently submit your design materials in a secure and private setting, and our expert engineers will provide individualized feedback to enhance your design. MicroCHECK design review service is subject to Microchip's [Program Terms and Conditions](https://www.microchip.com/en-us/support/design-help/design-check-services/design-check-services-program-terms-and-conditions) and requires a myMicrochip account.

The KSZ8795 is a highly-integrated, Layer 2-managed, 5-port switch with numerous features designed to reduce system cost. It is intended for cost-sensitive applications requiring four 10/100Mbps copper ports and one 10/100/1000Mbps Gigabit uplink port. The KSZ8795CLX incorporates a small package outline, lowest power consumption with internal biasing, and on-chip termination. Its extensive features set includes enhanced power management, programmable rate limiting and priority ratio, tagged and port-based VLAN, port-based security and ACL rule-based packet filtering technology, quality-of-service (QoS) priority with four queues, management interfaces, enhanced MIB counters, high-performance memory bandwidth, and a shared memory-based switch fabric with non-blocking support. The KSZ8795CLX provides support for multiple CPU data interfaces to effectively address both current and emerging fast Ethernet and Gigabit Ethernet applications where the port 5 GMAC can be configured to any of GMII, RGMII, MII and RMII modes. The KSZ8795CLX product is built upon Microchip's industry-leading Ethernet latest analog and digital technology, with features designed to offload host processing and streamline your overall design. • Four integrated 10/100Base-T/TX MAC/PHYs • One integrated 10/100/1000Base-T/TX GMAC with selectable GMII, RGMII, MII, and RMII interfaces • Small 80-pin LQFP package A robust assortment of power-management features including energy-efficient Ethernet (EEE), PME, and wake-on-LAN (WoL) have been designed-in to satisfy energy-efficient environments. All registers in the MAC and PHY units can be managed through the SPI interface. MIIM PHY registers can be accessed through the MDC/MDIO interface. Microchip's complimentary and confidential [MicroCHECK](https://www.microchip.com/en-us/support/design-help/design-check-services) design review service, which offers insight from the initial concept to the final PCB layout, is available to customers who are using our products in their projects. You can confidently submit your design materials in a secure and private setting, and our expert engineers will provide individualized feedback to enhance your design. MicroCHECK design review service is subject to Microchip's [Program Terms and Conditions](https://www.microchip.com/en-us/support/design-help/design-check-services/design-check-services-program-terms-and-conditions) and requires a myMicrochip account.

The KSZ8841-series of single-port controllers includes PCI and non-PCI CPU interfaces. The KSZ8841-PMQL datasheet describes PCI CPU interface chips. KSZ8841-PMQL is PQFP package chip. For information on the non-PCI controller, refer to the KSZ8841-MQL datasheet. The KSZ8841-PMQL is a single port Fast Ethernet MAC chip with 32-bit/33MHz PCI processor interface. Fully compliant with IEEE 802.3u, it is also available in industrial temperature grades. The KSZ8841MQL has 32-, 16- or 8-bit generic host processor interface. Microchip's complimentary and confidential [MicroCHECK](https://www.microchip.com/en-us/support/design-help/design-check-services) design review service, which offers insight from the initial concept to the final PCB layout, is available to customers who are using our products in their projects. You can confidently submit your design materials in a secure and private setting, and our expert engineers will provide individualized feedback to enhance your design. MicroCHECK design review service is subject to Microchip's [Program Terms and Conditions](https://www.microchip.com/en-us/support/design-help/design-check-services/design-check-services-program-terms-and-conditions) and requires a myMicrochip account.

The KSZ8842-series of 2-port switches includes PCI and non-PCI CPU interfaces. The datasheet describes the KSZ8842-PMQL/PMBL PCI CPU interface chips. KSZ8842-PMQL is PQFP package chip, KSZ8842-PMBL is LFBGA package chip. For information on the KSZ8842-MQL/MBL CPU non-PCI interface switches, refer to the KSZ8842-MQL/MBL datasheet. The KSZ8842-PMQL/PMBL is the industry's first fully managed 2-port switch with a 32-bit/33MHz PCI processor interface. It is a proven, 4th generation, integrated Layer 2 switch that is compliant with the IEEE 802.3u standard. An industrial temperature grade version of the KSZ8842-PMQL/PMBL, also can be ordered the KSZ8842-PMQLI/PMBL AM. The KSZ8842-PMQL/PMBL can be configured as a switch or as a low-latency (<310 nanoseconds) repeater in latency-critical, embedded or industrial Ethernet applications. For industrial automation applications, the KSZ8842-PMQL/PMBL can run in half-duplex mode regardless of the application. The KSZ8842-PMQL/PMBL offers an extensive feature set that includes tag/port-based VLAN, quality of service (QoS) priority management, management information base (MIB) counters, and CPU control/data interfaces to effectively address Fast Ethernet applications. The KSZ8842-PMQL/PMBL contains two 10/100 transceivers with patented, mixed-signal, low-power technology three media access control (MAC) units, a direct memory access (DMA) channel, a high-speed, non-blocking, switch fabric, a dedicated 1K entry forwarding table, and an on-chip frame buffer memory. Microchip's complimentary and confidential [MicroCHECK](https://www.microchip.com/en-us/support/design-help/design-check-services) design review service, which offers insight from the initial concept to the final PCB layout, is available to customers who are using our products in their projects. You can confidently submit your design materials in a secure and private setting, and our expert engineers will provide individualized feedback to enhance your design. MicroCHECK design review service is subject to Microchip's [Program Terms and Conditions](https://www.microchip.com/en-us/support/design-help/design-check-services/design-check-services-program-terms-and-conditions) and requires a myMicrochip account.

The KSZ8851 is a single-port controller chip with a SPI or 8-/16-/32-bit non-PCI CPU interface. Available in 32-/48-/128-pin packages, the KSZ8851 is for applications requiring cost-effective, high-throughput Ethernet connectivity in traditional embedded systems with MCUs or MPUs. **•** KSZ8851SNL/SNLI: SPI interface, 32-pin package **•** KSZ8851-16MLL: 8-/16-bit host bus, 48-pin package **•** KSZ8851-16/32MQL: 16-/32-bit host bus, 48-pin package (-16MQL) or 128-pin package (-32MQL) The KSZ8851 is a single chip, mixed analog/digital device offering Wake-on-LAN technology for effectively addressing Fast Ethernet applications. It consists of a Fast Ethernet MAC controller, an 8-bit or 16-bit generic host processor interface and incorporates a unique dynamic memory pointer with 4-byte buffer boundary and a fully utilizable 18KB for both TX (allocated 6KB) and RX (allocated 12KB) directions in host buffer interface. The KSZ8851 is designed to be compliant with the appropriate IEEE 802.3u standards. An industrial temperature-grade version of the KSZ8851 is also available. Physical signal transmission and reception are enhanced through the use of analog circuitry, making the design more efficient and allowing for lower-power consumption. The KSZ8851 is designed using a low-power CMOS process that features a single 3.3V power supply with options for 1.8V, 2.5V or 3.3V VDD I/O. The device includes an extensive feature set that offers management information base (MIB) counters and CPU control/data interfaces with single shared data bus timing. The KSZ8851 includes unique cable diagnostics feature called LinkMD®. This feature determines the length of the cabling plant and also ascertains if there is an open or short condition in the cable. Accompanying software enables the cable length and cable conditions to be conveniently displayed. In addition, the KSZ8851 supports Hewlett Packard (HP) Auto-MDIX thereby eliminating the need to differentiate between straight or crossover cables in applications. Microchip's complimentary and confidential [MicroCHECK](https://www.microchip.com/en-us/support/design-help/design-check-services) design review service, which offers insight from the initial concept to the final PCB layout, is available to customers who are using our products in their projects. You can confidently submit your design materials in a secure and private setting, and our expert engineers will provide individualized feedback to enhance your design. MicroCHECK design review service is subject to Microchip's [Program Terms and Conditions](https://www.microchip.com/en-us/support/design-help/design-check-services/design-check-services-program-terms-and-conditions) and requires a myMicrochip account.

The KSZ8862M is 2-port switch with fiber support, available in 8-/16-bit and 32-bit bus designs. The KSZ8862M is an industry first, fully managed, 2-port switch. It is based on a proven, 4th generation, integrated Layer-2 switch, compliant with IEEE 802.3u standards. For industrial applications, the KSZ8862M can run in half-duplex mode regardless of the application. In fiber mode, port 1 can be configurable to either 100BASE-FX or 100BASE-SX/10BASE-FL. The LED driver and post amplifier are also included for 10Base-FL and 100Base-SX applications. In copper mode, port 2 supports 10/100BASE-T/TX with HP Auto MDI/MDI-X for reliable detection of and correction for straight-through and crossover cables. Microchip's proprietary LinkMD® Time Domain Reflectometry (TDR) based function is also available for determining the cable length, as well as cable diagnostics for identifying faulty cabling. The KSZ8862M offers an extensive feature set that includes tag/port-based VLAN, quality of service (QoS) priority management, management information base (MIB) counters, and CPU control/data interfaces to effectively address Fast Ethernet applications. The KSZ8862M contains: • Two 10/100 transceivers with patented, mixed-signal, low-power technology • Two media access control (MAC) units • Direct memory access (DMA) channel • High-speed, non-blocking, switch fabric • Dedicated 1K entry forwarding table • On-chip frame buffer memory When using the provided KSZ8462 software driver, please exclude the 1588 PTP code at compile time. Microchip's complimentary and confidential [MicroCHECK](https://www.microchip.com/en-us/support/design-help/design-check-services) design review service, which offers insight from the initial concept to the final PCB layout, is available to customers who are using our products in their projects. You can confidently submit your design materials in a secure and private setting, and our expert engineers will provide individualized feedback to enhance your design. MicroCHECK design review service is subject to Microchip's [Program Terms and Conditions](https://www.microchip.com/en-us/support/design-help/design-check-services/design-check-services-program-terms-and-conditions) and requires a myMicrochip account.