Microchip Technology

The KSZ9031 is a completely integrated triple-speed (10Base-T/100Base-TX/1000Base-T) Ethernet physical-layer transceiver for transmission and reception of data on standard CAT-5 unshielded twisted pair (UTP) cable. The KSZ9031MNX offers the industry-standard GMII/MII (Gigabit Media Independent Interface/Media Independent Interface) for connection to GMII/MII MACs in Gigabit Ethernet processors and switches for data transfer at 1000Mbps or 10/100Mbps. The KSZ9031RNX provides the reduced gigabit media independent interface (RGMII). The KSZ9031 reduces board cost and simplifies board layout by using on-chip termination resistors for the four differential pairs and by integrating an LDO controller to drive a low-cost MOSFET to supply the 1.2V core. The KSZ9031 offers diagnostic features to facilitate system bring-up and debugging in production testing and in product deployment. Parametric NAND tree support enables fault detection between KSZ9031 I/Os and the board. The LinkMD® TDR-based cable diagnostic identifies faulty copper cabling. Remote and local loopback functions verify analog and digital data paths. The standard KSZ9031RNX is available in the 48-pin, lead-free QFN package, and the AEC-Q100 automotive qualified parts, KSZ9031RNXUB-VAO and KSZ9031RNXVB-VAO, are available in the 48-pin lead-free WQFN package. The KSZ9031MNX is available in a 64-pin, lead-free QFN package. Microchip's complimentary and confidential [MicroCHECK](https://www.microchip.com/en-us/support/design-help/design-check-services) design review service, which offers insight from the initial concept to the final PCB layout, is available to customers who are using our products in their projects. You can confidently submit your design materials in a secure and private setting, and our expert engineers will provide individualized feedback to enhance your design. MicroCHECK design review service is subject to Microchip's [Program Terms and Conditions](https://www.microchip.com/en-us/support/design-help/design-check-services/design-check-services-program-terms-and-conditions) and requires a myMicrochip account.

The KSZ9131 is a completely integrated triple-speed (10Base-T/100Base-TX/1000Base-T) Ethernet physical-layer transceiver for transmission and reception of data on standard CAT-5, CAT-5e and CAT6 unshielded twisted pair (UTP) cable. The KSZ9131RNX provides Reduced Gigabit Media Independent Interface RGMII and the KSZ9131MNX offers the industry-standard GMII/MII (Gigabit Media Independent Interface/Media Independent Interface) for connection to GMII/MII MACs in Gigabit Ethernet processors and switches for data transfer at 1000Mbps or 10/100Mbps. The KSZ9131 reduces board cost and simplifies board layout by using on-chip termination resistors for the four differential pairs and by integrating an LDO controller to drive a low-cost MOSFET to supply the 1.2V core. The KSZ9131 offers diagnostic features to facilitate system bring-up and debugging in production testing and in product deployment. Parametric NAND tree support enables fault detection between KSZ9131 I/Os and the board. The LinkMD® TDR-based cable diagnostic identifies faulty copper cabling. Remote and local loopback functions verify analog and digital data paths. The standard KSZ9131RNX is available in the 48-pin, RoHS compliant QFN package, and the AEC-Q100 automotive qualified parts, KSZ9131RNXU and KSZ9131RNXV, are available in the 48-pin lead-RoHS compliant VQFN (wettable) package. The KSZ9131MNX is available in a 64-pin, RoHS Compliant QFN package. Microchip's complimentary and confidential [MicroCHECK](https://www.microchip.com/en-us/support/design-help/design-check-services) design review service, which offers insight from the initial concept to the final PCB layout, is available to customers who are using our products in their projects. You can confidently submit your design materials in a secure and private setting, and our expert engineers will provide individualized feedback to enhance your design. MicroCHECK design review service is subject to Microchip's [Program Terms and Conditions](https://www.microchip.com/en-us/support/design-help/design-check-services/design-check-services-program-terms-and-conditions) and requires a myMicrochip account.

The KSZ9477 is a fully integrated layer 2, managed, seven-port gigabit Ethernet switch with numerous advanced features. Five of the seven ports incorporate 10/100/1000 Mbps PHYs. The other two ports have interfaces that can be configured as SGMII, RGMII, MII or RMII. Either of these may connect directly to a host processor or to an external PHY. The SGMII port may interface to a fiber optic transceiver. Full register access is available by SPI or I²C interfaces, and by optional in-band management via any of the data ports. PHY register access is provided by a MIIM interface. Security features include support for IEEE 802.1X port-based authentication and Access Control List (ACL) filtering. As a member of the EtherSynch® product family, the KSZ9477 incorporates full hardware support for the IEEE 1588v2 Precision Time Protocol (PTP), including hardware time-stamping at all PHY-MAC interfaces, and a high-resolution hardware "PTP clock". IEEE 1588 provides sub-microsecond synchronization for a range of industrial Ethernet applications. The KSZ9477 supports time-stamping and time-keeping features support IEEE 802.1AS time synchronization. All ports feature credit based traffic shapers for IEEE 802.1Qav. The KSZ9477 also incorporates features that simplify the implementation of DLR and HSR redundancy protocols by off-loading tasks from the host processor. For DLR networks, these features include Beacon frame generation, Beacon timeout detection, and MAC table flushing. HSR networks are supported with automatic duplicate frame discard, and self-address filtering. An assortment of power-management features including Energy-Efficient Ethernet (EEE) have been designed in to satisfy energy efficient environments. Looking for a Linux® Host Processor, try the [SAMA5D3](https://www.microchip.com/en-us/products/microcontrollers-and-microprocessors/32-bit-mpus/sama5/sama5d3-series). Microchip's complimentary and confidential [MicroCHECK](https://www.microchip.com/en-us/support/design-help/design-check-services) design review service, which offers insight from the initial concept to the final PCB layout, is available to customers who are using our products in their projects. You can confidently submit your design materials in a secure and private setting, and our expert engineers will provide individualized feedback to enhance your design. MicroCHECK design review service is subject to Microchip's [Program Terms and Conditions](https://www.microchip.com/en-us/support/design-help/design-check-services/design-check-services-program-terms-and-conditions) and requires a myMicrochip account.

The KSZ9563 is a highly-integrated, IEEE 802.3 compliant networking device that incorporates a layer-2+ managed Gigabit Ethernet switch, two 10BASE-T/100BASE-TX/1000BASE-T physical layer transceivers (PHYs) and associated MAC units, and one MAC port with a configurable RGMII/MII/RMII interface for direct connection to a host processor/ controller, another Ethernet switch, or an Ethernet PHY transceiver. KSZ9563 also implements IEEE 1588v2 Precision Timing Protocol. Full register access is available by SPI or I²C interfaces, and by optional in-band management via any of the data ports. PHY register access is provided by a MIIM interface. Security features include support for IEEE 802.1X port-based authentication and Access Control List (ACL) filtering. An assortment of power-management features including Energy-Efficient Ethernet (EEE) have been designed in to satisfy energy efficient environments. Looking for a Linux® Host Processor, try the [SAMA5D3](https://www.microchip.com/en-us/products/microprocessors/32-bit-mpus/sama5/sama5d3-series) Microchip's complimentary and confidential [MicroCHECK](https://www.microchip.com/en-us/support/design-help/design-check-services) design review service, which offers insight from the initial concept to the final PCB layout, is available to customers who are using our products in their projects. You can confidently submit your design materials in a secure and private setting, and our expert engineers will provide individualized feedback to enhance your design. MicroCHECK design review service is subject to Microchip's [Program Terms and Conditions](https://www.microchip.com/en-us/support/design-help/design-check-services/design-check-services-program-terms-and-conditions) and requires a myMicrochip account.

The KSZ9567 is a fully integrated layer 2, managed, seven-port gigabit Ethernet switch with numerous advanced features. Five of the seven ports incorporate 10/100/1000 Mbps PHYs. The other two ports have interfaces that can be configured as SGMII, RGMII, MII or RMII. Either of these may connect directly to a host processor or to an external PHY. The SGMII port may interface to a fiber optic transceiver. Full register access is available by SPI or I²C interfaces, and by optional in-band management via any of the data ports. PHY register access is provided by a MIIM interface. Security features include support for IEEE 802.1X port-based authentication and Access Control List (ACL) filtering. As a member of the EtherSynch® product family, the KSZ9567 incorporates full hardware support for the IEEE 1588v2 Precision Time Protocol (PTP), including hardware time-stamping at all PHY-MAC interfaces, and a high-resolution hardware "PTP clock". IEEE 1588 provides sub-microsecond synchronization for a range of industrial Ethernet applications. The KSZ9567 fully supports time-stamping and time-keeping features support IEEE 802.1AS time synchronization. All ports feature credit based traffic shapers for IEEE 802.1Qav, and a time aware scheduler as proposed for IEEE 802.1Qbv. An assortment of power-management features including Energy-Efficient Ethernet (EEE) have been designed in to satisfy energy efficient environments. Looking for a Linux® Host Processor, try the [SAMA5D3](https://www.microchip.com/en-us/products/microcontrollers-and-microprocessors/32-bit-mpus/sama5/sama5d3-series). Microchip's complimentary and confidential [MicroCHECK](https://www.microchip.com/en-us/support/design-help/design-check-services) design review service, which offers insight from the initial concept to the final PCB layout, is available to customers who are using our products in their projects. You can confidently submit your design materials in a secure and private setting, and our expert engineers will provide individualized feedback to enhance your design. MicroCHECK design review service is subject to Microchip's [Program Terms and Conditions](https://www.microchip.com/en-us/support/design-help/design-check-services/design-check-services-program-terms-and-conditions) and requires a myMicrochip account.

The KSZ9893 is a fully integrated layer 2, managed, three-port gigabit Ethernet switch with numerous advanced features. Two of the three ports incorporate 10/100/1000 Mbps PHYs. The other port has interfaces that can be configured as RGMII, MII or RMII. This port may connect directly to a host processor or to an external PHY. Full register access is available by SPI or I²C interfaces, and by optional in-band management via any of the data ports. PHY register access is provided by a MIIM interface. Security features include support for IEEE 802.1X port-based authentication and Access Control List (ACL) filtering. An assortment of power-management features including Energy-Efficient Ethernet (EEE) have been designed in to satisfy energy efficient environments. Looking for a Linux® Host Processor? Try the [SAMA5D3](https://www.microchip.com/en-us/products/microcontrollers-and-microprocessors/32-bit-mpus/sama5/sama5d3-series) Microchip's complimentary and confidential [MicroCHECK](https://www.microchip.com/en-us/support/design-help/design-check-services) design review service, which offers insight from the initial concept to the final PCB layout, is available to customers who are using our products in their projects. You can confidently submit your design materials in a secure and private setting, and our expert engineers will provide individualized feedback to enhance your design. MicroCHECK design review service is subject to Microchip's [Program Terms and Conditions](https://www.microchip.com/en-us/support/design-help/design-check-services/design-check-services-program-terms-and-conditions) and requires a myMicrochip account.

The KSZ9896 is a fully integrated layer 2, managed, six-port gigabit Ethernet switch with numerous advanced features. Five of the six ports incorporate 10/100/1000 Mbps PHYs. The sixth port has a MAC interface that can be configured as GMII, RGMII, MII or RMII. Full register access is available by SPI or I²C interfaces, and by optional in-band management via any of the data ports. PHY register access is provided by a MIIM interface. Security features include support for IEEE 802.1X port-based authentication and Access Control List (ACL) filtering. An assortment of power-management features including Energy-Efficient Ethernet (EEE) have been designed in to satisfy energy efficient environments. Microchip's complimentary and confidential [MicroCHECK](https://www.microchip.com/en-us/support/design-help/design-check-services) design review service, which offers insight from the initial concept to the final PCB layout, is available to customers who are using our products in their projects. You can confidently submit your design materials in a secure and private setting, and our expert engineers will provide individualized feedback to enhance your design. MicroCHECK design review service is subject to Microchip's [Program Terms and Conditions](https://www.microchip.com/en-us/support/design-help/design-check-services/design-check-services-program-terms-and-conditions) and requires a myMicrochip account.

The KSZ9897 is a fully integrated layer 2, managed, seven-port gigabit Ethernet switch with numerous advanced features. Five of the seven ports incorporate 10/100/1000 Mbps PHYs. The other two ports have interfaces that can be configured as SGMII, RGMII, MII or RMII. Either of these may connect directly to a host processor or to an external PHY. Full register access is available by SPI or I²C interfaces, and by optional in-band management via any of the data ports. PHY register access is provided by a MIIM interface. Security features include support for IEEE 802.1X port-based authentication and Access Control List (ACL) filtering. An assortment of power-management features including Energy-Efficient Ethernet (EEE) have been designed in to satisfy energy efficient environments. Software support is provided through Linux DSA and the Microchip GitHub. Looking for a Linux® Host Processor, try the [SAMA5D3](https://www.microchip.com/en-us/products/microcontrollers-and-microprocessors/32-bit-mpus/sama5/sama5d3-series). Microchip's complimentary and confidential [MicroCHECK](https://www.microchip.com/en-us/support/design-help/design-check-services) design review service, which offers insight from the initial concept to the final PCB layout, is available to customers who are using our products in their projects. You can confidently submit your design materials in a secure and private setting, and our expert engineers will provide individualized feedback to enhance your design. MicroCHECK design review service is subject to Microchip's [Program Terms and Conditions](https://www.microchip.com/en-us/support/design-help/design-check-services/design-check-services-program-terms-and-conditions) and requires a myMicrochip account.

These super hyperabrupt varactor diodes are ideal for tuning LC resonant circuits from video frequencies through VHF with frequency ratios as high as 4 to 1. They are also ideal for wide deviation voltage controlled oscillators and voltage controlled crystal oscillators. Two volt capacitance values range from 57 to 350 pF are offered in this designer-oriented family. These diodes feature exceptionally large capacitance ratios, very high Q, straight-line frequency performance over a 1.5 to 4 volt tuning range.