KSZ8765 Series
5-Port 10/100 Managed Ethernet Switch with Fiber Support
Manufacturer: Microchip Technology
Catalog
5-Port 10/100 Managed Ethernet Switch with Fiber Support
Key Features
• Integrated 5-port 10/100 Layer-2 switch with Gigabit uplink
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• New generation switch with four MACs, one GMAC (for uplink) and four PHYs (two 10/100Base-T/TX & two 100Base-FX) that are fully compliant with the IEEE 802.3u standard
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• 10/100Base-T/TX & 100Base-FX switch system which combines a switch engine, frame buffer management, address lookup table, queue management, MIB counters, MAC, and PHY transceivers
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• Rapid spanning tree support (RSTP) for topology management
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• Microchip LinkMD® cable diagnostic capabilities for determining cable opens, shorts, and length
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• Advanced Switch Capabilities
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• IEEE 802.1q VLAN support for up to 128 active VLAN groups (full range 4096 of VLAN IDs)
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• Support 802.1x port-based security and MAC-based authentication via access control lists (ACL)
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• QoS/CoS Packet Prioritization Support
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• 802.1p, DiffServ-based and Re-mapping of 802.1p priority field, per-port basis on four priority levels
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• 4 priority queues with dynamic mapping for IEEE 802.1P, IPV4 ToS (DiffServ), IPV6 Traffic Class, etc.
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• Programmable rate limiting at the ingress and egress ports on a per port basis
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• Comprehensive Configuration Register Access
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• High-speed SPI (4-wire, up to 50MHz) interface to access all internal registers
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• MII management (MIIM, MDC/MDIO 2 wire) interface to access all PHY registers per IEEE 802.3 specification
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• Control registers configurable on-the-fly
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• Switch Monitoring Features
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• Port mirroring/monitoring/sniffing: ingress and/or egress traffic to any port or MII/RMII
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• MIB counters for fully-compliant statistics gathering (36 MIB counters per port)
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• Low Power Dissipation
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• Full-chip software power-down
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• Energy detect power-down (EDPD)
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• Support IEEE P802.3az Energy Efficient Ethernet (EEE)
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• Wake on LAN (WoL) support
Description
AI
The KSZ8765 is a highly integrated, Layer 2-managed, five-port switch with numerous features designed to reduce overall system cost. It is intended for cost-sensitive applications requiring four 10/100Mbps copper ports and one 10/100/1000Mbps Gigabit uplink port.
The KSZ8765CLX incorporates a small package outline, low power consumption with internal biasing, and on-chip termination. Its extensive set of features include enhanced power management, programmable rate limiting and priority ratio, tagged and port-based VLAN, port-based security and ACL rule-based packet filtering technology, QoS priority with four queues, management interfaces, enhanced MIB counters, high-performance memory bandwidth, and a shared memory-based switch fabric with non-blocking support.
The KSZ8765CLX provides support for multiple CPU data interfaces to effectively address both current and emerging fast Ethernet and Gigabit Ethernet applications where the Port 5 GMAC can be configured to any of the GMII, RGMII, MII, and RMII modes. The KSZ8765CLX is built upon Microchip's industry-leading Ethernet analog and digital technology, with features designed to offload host processing and streamline the overall design.
• Two integrated MAC/PHYs 100Base-FX on Port 1 and Port 2
• Two integrated MAC/PHYs 10/100Base-T/TX on Port 3 and Port 4
• One integrated 10/100/1000Base-T/TX GMAC with selectable GMII, RGMII, MII, and RMII interfaces
• Small 80-pin LQFP package
A robust assortment of power management features including energy-efficient Ethernet (EEE), power management event (PME), and wake-on-LAN (WoL) have been designed in to satisfy energy efficient environments. All registers in the MAC/PHY units can be managed through the SPI interface. MIIM PHY registers can be accessed through the MDC/MDIO interface.
Microchip's complimentary and confidential [MicroCHECK](https://www.microchip.com/en-us/support/design-help/design-check-services) design review service, which offers insight from the initial concept to the final PCB layout, is available to customers who are using our products in their projects. You can confidently submit your design materials in a secure and private setting, and our expert engineers will provide individualized feedback to enhance your design. MicroCHECK design review service is subject to Microchip's [Program Terms and Conditions](https://www.microchip.com/en-us/support/design-help/design-check-services/design-check-services-program-terms-and-conditions) and requires a myMicrochip account.