Microchip Technology

The SY10/100ELT22 are dual TTL-to-differential PECL translators. Because PECL (Positive ECL) levels are used, only +5V and ground are required. The small outline 8-lead SOIC package and the low skew, dual gate design of the ELT22 makes it ideal for applications which require the tranlation of a clock and a data signal.The ELT22 is available in both ECL standards: the 10ELT is compatible with positive ECL 10H logic levels, while the 100ELT is compatible with positive ECL 100K logic levels.

The 100ELT23L are dual differential LVPECL-to-LVTTL translators with +3.3V power supply. Because LVPECL (Low Voltage Positive ECL) levels are used, only +3.3V and ground are required. The small outline 8-lead SOIC package and the low skew, dual gate design of the ELT23L makes it ideal for applications which require the tranlation of a clock and a data signal.The ELT23L is compatible with positive ECL 100K logic levels.

The SY100ELT25 is a differential ECL-to-TTL translator. Because ECL levels are used, a +5V, -5.2V (or -4.5V) and ground are required. The small outline 8- lead SOIC package and the single gate of the ELT25 makes it ideal for those applications where performance, space and low power are at a premium.The VBB output allows the ELT25 to also be used in a single-ended input mode. In this mode the VBB output is tied to the D input for a non-inverting buffer or the D input for an inverting buffer. If used the VBB pin should be bypassed to ground via a 0.01µF capacitor.

The SY100EP56V is a high-speed, low-skew, fully differential Dual PECL/ECL 2:1 multiplexer. This device is a pin-for-pin, plug-in replacement to the MC10/100EP56DT. Two separate 2:1 multiplexers (Channel 0 and Channel 1) with dedicated select control pins (SEL0 and SEL1) are implemented in a 20-pin TSSOP package. The signal-path inputs (D0a, D0b and D1a, D1b) accept differential signals as low as 150mV pk-pk. For applications that require common select control for both channels A & B, a common select pin (COM\_SEL) is available. All I/O pins are 100k PECL/ECL logic compatible. AC–performance is guaranteed over the industrial –40°C to +85°C temperature range and 3.0V to 5.5V supply voltage range. This device will operate in PECL/LVPECL or ECL/ LVECL mode. The 500ps max (400 typ) propagation delay is matched for all signal and logic select paths: D-to-QOUT, SEL-to-QOUT, and COM\_SEL-to-QOUT. Two VBB output reference pins (approx equal to VCC –1.4V) are available for AC–coupled or single-ended applications. The SY100EP56V is part of Micrel’s high-speed, Precision Edge timing and distribution family. For applications that require a different I/O combination, consult the Micrel website at www.micrel.com, and choose from a comprehensive product line of high-speed, low skew fanout buffers, translators, and clock dividers.

The SY100EP57V is a high-speed, low-skew, fully differential PECL/ECL 4:1 multiplexer in a 20-pin TSSOP package. This device is a pin-for-pin, plug-in replacement to the MC10/100EP57DT. The signal-path inputs (D0:D3) accept differential signals as low as 150mVpk-pk. All I/O pins are 100K EP PECL/ECL logic compatible. AC–performance is guaranteed over the industrial –40°C to +85°C temperature range and 3.0V to 5.5V supply voltage range. This device will operate in PECL/LVPECL or ECL/ LVECL mode. The SY100EP57 propagation delay is less than 520ps, and the Select-to-valid output delay is less than 575ps over temperature and voltage. For clock applications, the high-speed design combined with an extremely fast rise/fall time of less than 220ps produces a toggle frequency as high as 3GHz (400mVpk-pk swing). Two VBB output reference pins (approx equal to VCC–1.4V) are available for AC–coupled or single-ended applications. The SY100EP57V is part of Micrel’s high-speed, Precision Edge timing and distribution family. For applications that require a different I/O combination, consult the Micrel website at www.micrel.com, and choose from a comprehensive product line of high-speed, low skew fanout buffers, translators, and clock dividers.

The SY100EPT20 is a TTL/CMOS to differential PECL translator. Capable of running from a 3.3 or 5V supply, the part can be used in either LVTTL/LVCMOS/ LVPECL or TTL/CMOS/PECL systems. The device only requires a single positive supply of 3.3V or 5V - no negative supply is required. The tiny 8-pin MSOP package and the low skew, dual gate design of the EPT20V makes it ideal for those applications where space, performance, and low power are at a premium.