Microchip Technology

The SY100EPT22V is a dual TTL/CMOS to differential PECL translator. Capable of running from a 3.3 or 5V supply, the part can be used in either LVTTL/LVCMOS/ LVPECL or TTL/CMOS/PECL systems. The device only requires a single positive supply of 3.3V or 5V - no negative supply is required. The tiny 8-pin MSOP package and the low skew, dual gate design of the EPT22V makes it ideal for those applications where space, performance, and low power are at a premium.

The SY100EPT23L is a dual differential LVPECL-to-LVTTL translator. Because LVPECL (Low Voltage Positive ECL) levels are used, only +3.3V and ground are required. The tiny 8-pin MSOP and dual-gate design of the EPT23L makes it ideal for applications which require the translation of a clock and data signal. The EPT23L is available in only the ECL 100K standard. Since there are no LVPECL outputs or an external VBB reference, the EPT23L does not require both ECL standard versions. The inputs can accept 10K voltage levels and any standard differential LVPECL input referenced from a VCC of +3.3V.

1011GN-125EL-POWER-TRANSISTOR

1011GN-2200VP-Power-Transistor

The 1011GN-30E/EL/EP is a 30 Watts, 50 Volts, 1030-1090 MHz, Earless Driver GaN Transistor. This 30 W device features 128μs, 10% signaling with 30W Pulsed Output Power, plus 32μS-2% Pulsing. Designed using Common Source, class AB devices, the product utilizes 50V Bias Voltage and offers a >60% efficiency across the frequency band. The transistor is available in an extremely compact size with 18.5 dB typical power gain and 0.3 dB typical gain flatness. Ideal for use in IFF, Mode-S, TCAS Avionics Secondary Radars. All gold metallization and eutectic die attach for highest reliability. 50Ω in/out lumped element, very small footprint, plug & play pallets available.

The SY10EP51V is a D flip-flop with reset and differential clock. The device is pin and functionally equivalent to the EL51 device.The reset input is an asynchronous, level triggered signal. Data enters the master portion of the flip-flop when CLK is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the CLK. The differential clock inputs of the EP51V allow the device to be used as a negative edge triggered flip-flop.The differential input employs clamp circuitry to maintain stability under open input conditions. When left open, the CLK input will be pulled down to VEE and the /CLK input will be biased a VCC/2.