Microchip Technology

The SY100EL17V is a quad differential receiver. The device is functionally equivalent to the E116 device with the capability of operation from either a ECL supply voltage (-3.3V or -5V) or PECL supply voltage (+3.3V or +5V).The EL17V provides a VBB output for either single-ended use or as a DC bias for AC coupling to the device. The VBBpin should be used only as a bias for the EL17V as its current sink/source capability is limited.Whenever used, the VBB pin should be bypassed to ground via a 0.01µf capacitor.Under open input conditions, the /D input will be biased at VCC/2 and the D input will be pulled down to VEE. This operation will force the Q output LOW and ensure stability.

The SY100EL32V is an integrated divide by 2 divider. The differential clock inputs and the VBB allow a differential, single-ended or AC-coupled interface to the device. If used, the VBB output should be bypassed to ground with a 0.01 µF capacitor. Also note that the VBB is designed to be used as an input bias on the EL32V only; the VBB output has limited current sink and source capability. The Reset pin is asynchronous and is asserted on the rising edge. Upon power-on, the internal flip-flop will attain a random state. The Reset allows for the synchronization of multiple EL32Vs in a system.

The SY10/100EL52 are differential data, differential clock D flip-flops. These devices are functionally equivalent to the E452 devices, with higher performance capabilities. With propagation delays and output transition times significantly faster than the E452, the EL52 is ideally suited for those applications which require the ultimate in AC performance.Data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock.The differential clock inputs also allow the EL52 to be used as a negative edge triggered device.The EL52 employs input clamping circuitry so that, under open input conditions (pulled down to VEE), the outputs of the device will remain stable.

The SY100EL90V is a triple ECL/LVECL-to-PECL/LVPECL translator. The device can translate over all combinations of supply voltages: -5V ECL to 5V PECL, -5V ECL to 3.3V LVPECL, -3.3V LVECL to 5V PECL or -3.3V LVECL to 3.3V LVPECL.A VBB output is provided for interfacing with single ended ECL signals at the input. If a single ended input is to be used, the VBB output should be connected to the D input. The active signal would then drive the D input. When used, the VBBoutput should be bypassed to via a 0.01µF capacitor. The VBB output is designed to act as the switching reference for the EL90V under single ended input switching conditions. As a result this pin can only source/sink up to 0.5mA of current. To accomplish the level translation the EL90V requires three power rails. The VCC supply should be connected to the positive supply, and the VEE pin should be connected to the negative power supply. The GND pins as expected are connected to the system ground plane. Both VEE and VCC should be bypassed to ground via 0.01µF capacitors.Under open input conditions, the D input will be biased at VCC/2 and the D input will be pulled to VEE. This condition will force the Q output to a LOW, ensuring stability.

The SY100EL91L is a triple LVPECL-to-ECL or LVPECL-to-LVECL translator. A VBB output is provided for interfacing with single ended PECL signals at the input. If a single ended input is to be used, the VBB output should be connected to the D input. The active signal would then drive the D input. When used, the VBB output should be bypassed to ground via a 0.01µF capacitor. The VBB output is designed to act as the switching reference for the EL91L under single ended input switching conditions. As a result this pin can only source/sink up to 0.5mA of current.To accomplish the level translation the EL91L requires three power rails. The VCC supply should be connected to the positive supply, and the VEE pin should be connected to the negative power supply. The GND pins as expected are connected to the system ground plane. Both VEE and VCC should be bypassed to ground via 0.01µF capacitors.Under open input conditions, the D input will be biased at VCC/2 and the D input will be pulled to GND. This condition will force the Q output to a LOW, ensuring stability.

The SY100ELT21L is a single differential LVPECL to- LVTTL translator s using a single +3.3V power supply. Because LVPECL (Low Voltage Positive ECL) levels are used, only +3.3V and ground are required. The small outline 8-lead SOIC package and low skew single gate design make the ELT21L ideal for applications that require the translation of a clock or data signal where minimal space, low power, and low cost are critical. VBB allows a differential, single-ended, or AC-coupled interface to the device. If used, the VBB output should be bypassed to VCC with 0.01µF capacitor. Under open input conditions, the /D will be biased at a VCC/2 voltage level and the D input will be pulled to ground. This condition will force the Q output low to provide added stability. The 100ELT is compatible with positive ECL 100K logic levels.