| Integrated Circuits (ICs) | 5 | Active | The SY100EP56V is a high-speed, low-skew, fully differential Dual PECL/ECL 2:1 multiplexer. This device is a pin-for-pin, plug-in replacement to the MC10/100EP56DT. Two separate 2:1 multiplexers (Channel 0 and Channel 1) with dedicated select control pins (SEL0 and SEL1) are implemented in a 20-pin TSSOP package. The signal-path inputs (D0a, D0b and D1a, D1b) accept differential signals as low as 150mV pk-pk. For applications that require common select control for both channels A & B, a common select pin (COM\_SEL) is available. All I/O pins are 100k PECL/ECL logic compatible. AC–performance is guaranteed over the industrial –40°C to +85°C temperature range and 3.0V to 5.5V supply voltage range. This device will operate in PECL/LVPECL or ECL/ LVECL mode. The 500ps max (400 typ) propagation delay is matched for all signal and logic select paths: D-to-QOUT, SEL-to-QOUT, and COM\_SEL-to-QOUT. Two VBB output reference pins (approx equal to VCC –1.4V) are available for AC–coupled or single-ended applications. The SY100EP56V is part of Micrel’s high-speed, Precision Edge timing and distribution family. For applications that require a different I/O combination, consult the Micrel website at www.micrel.com, and choose from a comprehensive product line of high-speed, low skew fanout buffers, translators, and clock dividers. |
| Signal Switches, Multiplexers, Decoders | 3 | Active | The SY100EP57V is a high-speed, low-skew, fully differential PECL/ECL 4:1 multiplexer in a 20-pin TSSOP package. This device is a pin-for-pin, plug-in replacement to the MC10/100EP57DT. The signal-path inputs (D0:D3) accept differential signals as low as 150mVpk-pk. All I/O pins are 100K EP PECL/ECL logic compatible. AC–performance is guaranteed over the industrial –40°C to +85°C temperature range and 3.0V to 5.5V supply voltage range. This device will operate in PECL/LVPECL or ECL/ LVECL mode. The SY100EP57 propagation delay is less than 520ps, and the Select-to-valid output delay is less than 575ps over temperature and voltage. For clock applications, the high-speed design combined with an extremely fast rise/fall time of less than 220ps produces a toggle frequency as high as 3GHz (400mVpk-pk swing). Two VBB output reference pins (approx equal to VCC–1.4V) are available for AC–coupled or single-ended applications. The SY100EP57V is part of Micrel’s high-speed, Precision Edge timing and distribution family. For applications that require a different I/O combination, consult the Micrel website at www.micrel.com, and choose from a comprehensive product line of high-speed, low skew fanout buffers, translators, and clock dividers. |
| Integrated Circuits (ICs) | 7 | Active | The SY100EPT20 is
a TTL/CMOS to differential PECL translator. Capable of running from a 3.3 or 5V
supply, the part can be used in either LVTTL/LVCMOS/ LVPECL or TTL/CMOS/PECL
systems. The device only requires a single positive supply of 3.3V or 5V - no
negative supply is required. The tiny 8-pin MSOP package and the low skew, dual
gate design of the EPT20V makes it ideal for those applications where space,
performance, and low power are at a premium. |
| Logic | 7 | Active | The SY100EPT21L is a single, differential LVPECL-to-LVTTL translator using a single +3.3V power supply. Because low voltage positive ECL (LVPECL) levels are used, only +3.3V and ground are required. The small outline 8-pin SOIC package and low-skew, single-gate design make the EPT21L ideal for applications that require the translation of a clock or data signal where minimal space, low power, and low cost are critical.VBB allows a differential, single-ended, or AC-coupled interface to the device. If used, the VBB output should be bypassed to VCC with 0.01μF capacitor. Under open input conditions, the /D will be biased at a VCC/2 voltage level and the D input will be pulled to ground. This condition will force the Q output low to provide added stability.The 100EPT is compatible with positive ECL 100K logic levels. For applications that require the smallest footprint, consider the SY89321L in an ultra-small (2mm × 2mm) 8-pin MLF® package. |
| Translators, Level Shifters | 9 | Active | The SY100EPT22V is a dual TTL/CMOS to differential PECL translator. Capable of running from a 3.3 or 5V supply, the part can be used in either LVTTL/LVCMOS/ LVPECL or TTL/CMOS/PECL systems. The device only requires a single positive supply of 3.3V or 5V - no negative supply is required. The tiny 8-pin MSOP package and the low skew, dual gate design of the EPT22V makes it ideal for those applications where space, performance, and low power are at a premium. |
| Translators, Level Shifters | 8 | Active | The SY100EPT23L is a dual differential LVPECL-to-LVTTL translator. Because LVPECL (Low Voltage Positive ECL) levels are used, only +3.3V and ground are required. The tiny 8-pin MSOP and dual-gate design of the EPT23L makes it ideal for applications which require the translation of a clock and data signal. The EPT23L is available in only the ECL 100K standard. Since there are no LVPECL outputs or an external VBB reference, the EPT23L does not require both ECL standard versions. The inputs can accept 10K
voltage levels and any standard differential LVPECL input referenced from a VCC of +3.3V. |
| Clock Buffers, Drivers | 4 | Obsolete | |
| Clock/Timing | 2 | Obsolete | |
| Integrated Circuits (ICs) | 2 | Obsolete | |
| Integrated Circuits (ICs) | 4 | Active | The SY100S834/L is low skew (÷1, ÷2, ÷4) or (÷2, ÷4, ÷8) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. In addition, by using the VBB output, a sinusoidal source can be AC-coupled into the device. If a single-ended input is to be used, the VBB output should be connected to the CLK input and bypassed to ground via a 0.01µF capacitor. The VBB output is designed to act as the switching reference for the input of the SY100S834/L under single-ended input conditions. As a result, this pin can only source/sink up to 0.5mA of current.
The Function Select (FSEL) input is used to determine what clock generation chip function is. When FSEL input is LOW, SY100S834/L functions as a divide by 2, by 4 and by 8 clock generation chip. However, if FSEL input is HIGH, it functions as a divide by 1, by 2 and by 4 clock generation chip. This latter feature will increase the clock frequency by two folds.The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages.
The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input.Upon start-up, the internal flip-flops will attain a random state; the master reset (MR) input allows for the synchronization of the internal dividers, as well as for multiple SY100S834/Ls in a system. |
