Microchip Technology

The SY100EL15L is a low skew 1:4 clock distribution IC designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. If a single-ended input is to be used the VBB output should be connected to the CLK input and bypassed to ground via a 0.01µF capacitor. The VBB output is designed to act as the switching reference for the input of the EL15 under singleended input conditions. As a result, this pin can only source/sink up to 0.5mA of current. The EL15 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pull-down resistor) the SEL pin will select the differential clock input.The common enable (EN) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/ disabled as can happen with an asynchronous control.The internal flip flop is clocked on the falling edge of the input clock, therefore all associated specification limits are referenced to the negative edge of the clock input. When both differential inputs are left open, CLK input will pull down to VEE and CLK input will bias around VCC/2.

The SY100EL16VS are differential receivers with variable output swing. The devices are functionally equivalent to the EL16V devices with an input that control the amplitude of the outputs.The operational range of the EL16VS control input is from VBB (max. swing) to VCC (min. swing). Simple control of the output swing can be obtained by a variable resistor between the VBB pin and VCC with the wiper driving VCTRL.The EL16VS provides a VBB output for either single-ended use or as a DC bias for AC coupling to the device. The VBBpin should be used only as a bias for the EL16VS as its current sink/source capability is limited. Whenever used, the VBB pin should be bypassed to ground via a 0.01mF capacitor.Under open input conditions (pulled to VEE), internal input clamps will force the Q output LOW.

The SY100EL17V is a quad differential receiver. The device is functionally equivalent to the E116 device with the capability of operation from either a ECL supply voltage (-3.3V or -5V) or PECL supply voltage (+3.3V or +5V).The EL17V provides a VBB output for either single-ended use or as a DC bias for AC coupling to the device. The VBBpin should be used only as a bias for the EL17V as its current sink/source capability is limited.Whenever used, the VBB pin should be bypassed to ground via a 0.01µf capacitor.Under open input conditions, the /D input will be biased at VCC/2 and the D input will be pulled down to VEE. This operation will force the Q output LOW and ensure stability.

The SY100EL29V is a dual differential register with differential data (inputs and outputs) and clock. The registers are triggered by a positive transition of the positive clock (CLK) input. A HIGH on the Reset (Rx) asynchronously resets the appropriate register so that the Q outputs go LOW. A HIGH on the Set (Sx) asynchronously resets the appropriate register so that the Q outputs go HIGH. The Set and Reset inputs cannot both be HIGH simultaneously.The differential input structures are clamped so that the inputs of unused registers can be left open without upsetting the bias network of the devices. The clamping action will assert the /D and the /CLK sides of the inputs. The noninverting input will pull down to VEE and the inverting input will be biased around VCC/2. Because of the edge-triggered flip-flop nature of the devices, simultaneously opening both the clock and data inputs will result in an output which reaches an unidentified but valid state.The fully differential design of the devices makes them ideal for very high frequency applications where a registered data path is necessary.

The SY10/100EL52 are differential data, differential clock D flip-flops. These devices are functionally equivalent to the E452 devices, with higher performance capabilities. With propagation delays and output transition times significantly faster than the E452, the EL52 is ideally suited for those applications which require the ultimate in AC performance.Data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock.The differential clock inputs also allow the EL52 to be used as a negative edge triggered device.The EL52 employs input clamping circuitry so that, under open input conditions (pulled down to VEE), the outputs of the device will remain stable.

The SY100EL90V is a triple ECL/LVECL-to-PECL/LVPECL translator. The device can translate over all combinations of supply voltages: -5V ECL to 5V PECL, -5V ECL to 3.3V LVPECL, -3.3V LVECL to 5V PECL or -3.3V LVECL to 3.3V LVPECL.A VBB output is provided for interfacing with single ended ECL signals at the input. If a single ended input is to be used, the VBB output should be connected to the D input. The active signal would then drive the D input. When used, the VBBoutput should be bypassed to via a 0.01µF capacitor. The VBB output is designed to act as the switching reference for the EL90V under single ended input switching conditions. As a result this pin can only source/sink up to 0.5mA of current. To accomplish the level translation the EL90V requires three power rails. The VCC supply should be connected to the positive supply, and the VEE pin should be connected to the negative power supply. The GND pins as expected are connected to the system ground plane. Both VEE and VCC should be bypassed to ground via 0.01µF capacitors.Under open input conditions, the D input will be biased at VCC/2 and the D input will be pulled to VEE. This condition will force the Q output to a LOW, ensuring stability.

The SY100EL91L is a triple LVPECL-to-ECL or LVPECL-to-LVECL translator. A VBB output is provided for interfacing with single ended PECL signals at the input. If a single ended input is to be used, the VBB output should be connected to the D input. The active signal would then drive the D input. When used, the VBB output should be bypassed to ground via a 0.01µF capacitor. The VBB output is designed to act as the switching reference for the EL91L under single ended input switching conditions. As a result this pin can only source/sink up to 0.5mA of current.To accomplish the level translation the EL91L requires three power rails. The VCC supply should be connected to the positive supply, and the VEE pin should be connected to the negative power supply. The GND pins as expected are connected to the system ground plane. Both VEE and VCC should be bypassed to ground via 0.01µF capacitors.Under open input conditions, the D input will be biased at VCC/2 and the D input will be pulled to GND. This condition will force the Q output to a LOW, ensuring stability.

The SY100EL92 is a triple LVPECL-to-PECL or PECLto-LVPECL translator. The device receives standard PECL signals and translates them to differential LVPECL output signals (or vice versa). SY100EL92 can also be used as a differential line receiver for PECL-to-PECL or LVPECL-to-LVPECL signals. However, please note that for the latter we will need two different power supplies. Please refer to Function Table for more details.VBB outputs are provided for interfacing single ended input signals. If a single ended input is to be used, the VBB output should be connected to the D input and the active signal will drive the D input. When used, the VBB should be bypassed to VCC via a 0.01µF capacitor. The VBB is designed to act as a switching reference for the SY100EL92 under single ended input conditions. As a result, the pin can only source/sink 0.5mA of current.To accomplish the PECL-to-LVPECL level translation, the SY100EL92 requires three power rails. The VCC and VCC\_VBB supply is to be connected to the standard PECL supply, the 3.3V supply is to be connected to the VCCOsupply, and GND is connected to the system ground plane. Both the VCC and VCCO should be bypassed to ground with a 0.01µF capacitor.To accomplish the LVPECL-to-PECL level translation, the SY100EL92 requires three power rails as well. The 5.0V supply is connected to the VCC and VCCO pins, 3.3V supply is connected to the VCC\_VBB pin and GND is connected to the system ground plane. VCC\_VBB is used to provide a proper VBB output level if a single ended input is used. For differential LVPECL input VCC\_VBB can be either 3.3V or 5V.Under open input conditions, the D input will be biased at a VCC/2 voltage level and the D input will be pulled to GND. This condition will force the "Q" output low, ensuring stability.