| Logic | 8 | Active | The SY100ELT21L
is a single
differential LVPECL
to- LVTTL translator
s using
a single +3.3V power supply. Because LVPECL (Low Voltage Positive ECL) levels
are used, only +3.3V and ground are required. The small outline 8-lead SOIC
package and low skew single gate design make the ELT21L ideal for applications
that require the translation of a clock or data signal where minimal space, low
power, and low cost are critical. VBB allows
a differential, single-ended, or AC-coupled interface to the device. If used,
the VBB output should be bypassed to VCC with 0.01µF capacitor.
Under open
input conditions, the /D will be biased at a VCC/2 voltage level and the D
input will be pulled to ground. This condition will force the Q output low to
provide added stability. The 100ELT
is compatible with positive ECL 100K logic levels. |
| Logic | 10 | Active | The SY10/100ELT22 are dual TTL-to-differential PECL translators. Because PECL (Positive ECL) levels are used, only +5V and ground are required. The small outline 8-lead SOIC package and the low skew, dual gate design of the ELT22 makes it ideal for applications which require the tranlation of a clock and a data signal.The ELT22 is available in both ECL standards: the 10ELT is compatible with positive ECL 10H logic levels, while the 100ELT is compatible with positive ECL 100K logic levels. |
| Logic | 7 | Active | The 100ELT23L are dual differential LVPECL-to-LVTTL translators with +3.3V power supply. Because LVPECL (Low Voltage Positive ECL) levels are used, only +3.3V and ground are required. The small outline 8-lead SOIC package and the low skew, dual gate design of the ELT23L makes it ideal for applications which require the tranlation of a clock and a data signal.The ELT23L is compatible with positive ECL 100K logic levels. |
| Integrated Circuits (ICs) | 3 | Active | |
| Clock Buffers, Drivers | 4 | Active | The SY10/100EP11U is a precision, high-speed 1:2 differential fanout buffer. Having within-device skews and output transition times significantly improved over the EL11V, the EP11U is ideally suited for those applications which require the ultimate in AC performance.The differential inputs of the EP11U employ clamping circuitry to maintain stability under open input conditions. If the inputs are left open, the Q outputs will go LOW. |
| Clock Buffers, Drivers | 3 | Obsolete | |
| Clock Generators, PLLs, Frequency Synthesizers | 4 | Obsolete | |
| Clock Buffers, Drivers | 5 | Active | The SY100EP15V is a high-speed, low-skew, PECL/ECL 1:4 precision fanout buffer with a 2:1 mux front end in a small 16-pin TSSOP package. The 2:1 mux input accepts a single-ended PECL/ECL source (CLK1) and a differential PECL/ECL/HSTL source (CLK0). All I/O pins are 100K EP PECL/ECL logic compatible.
AC performance is guaranteed over the industrial –40°C to +85°C temperature range and 3.3V to 5V supply voltage. This device will operate in PECL/LVPECL or ECL/LVECL mode. For clock applications, the high-speed design combined with an extremely fast rise/fall time of less than 225ps produces a toggle frequency as high as 2.5GHz (~400mVPP swing).A VBB output reference pin is available for AC–coupled and single-ended input applications. In addition, a synchronous output enable function is provided.The SY100EP15V is part of Micrel’s high-speed, precision edge timing and distribution family.
For applications that require a different I/O combination, consult Micrel's website and choose from a comprehensive product line of high-speed, low-skew fanout buffers, translators, and clock dividers. |
| Delay Lines | 2 | Active | The SY100EP196V is a programmable delay line, varying the time a logic signal takes to traverse from IN to Q. This delay can vary from about 2.2ns to about 12.2ns. The input can be PECL, LVPECL, NECL, or LVNECL.The delay varies in discrete steps based on a control word presented to SY100EP196V. The 10-bit width of this latched control register allows for delay increments of approximately 10ps. In addition, delay may be varied continuously in about a 30ps range by setting the voltage at the FTUNE pin.An eleventh control bit allows the cascading of multiple SY100EP196V devices, for a wider delay range. Each additional SY100EP196V effectively doubles the delay range available.For maximum flexibility, the control register interface accepts CMOS or TTL level signals, as well as the input level at the IN± pins. |
| Clock/Timing | 1 | Active | |
