Analog Devices

The HMC941 devices are broadband, 5-bit, GaAs, IC digital attenuators available in a low cost, leadless, surface-mount package or in a monolithic microwave integrated circuit (MMIC) chip. Covering 0.1 GHz to 30 GHz or 33 GHz, the insertion loss is less than 4 dB typical. The attenuator bit values are 0.5 (LSB), 1, 2, 4, and 8 dB for a total attenuation of 15.5 dB. Attenuation accuracy is excellent at ±0.3 dB or less than ±0.5 dB typical step error with an IIP3 of +45 dBm. Five control voltage inputs, toggled between +5 V and 0 V, are used to select each attenuation state.ApplicationsFiber optics and broadband telecomMicrowave radio and VSATMilitary radios, radar, and ECMSpace applicationsSensorsTest and measurement equipment

The HMC943APM5E is a four stage, gallium arsenide (GaAs), pseudomorphic high electron mobility transistor (pHEMT), monolithic microwave integrated circuit (MMIC), >1.5 W power amplifier that operates between 24 GHz to 34 GHz. The HMC943APM5E provides 23 dB of gain, 34 dBm of saturated output power (PSAT), and 23% power added efficiency (PAE) from a 5.5 V supply. The high output third-order intercept (IP3) of 39 dBm makes the HMC943APM5E ideal for microwave radio applications. A power detector output is also available. The HMC943APM5E amplifier input/outputs (I/Os) are internally matched to 50 Ω. The device is packaged in a leadless, 5 mm × 5 mm, surface-mount LFCSP_CAV package, and requires no external matching components.ApplicationsPoint to point radiosPoint to multipoint radiosMicrowave radios, very small aperture terminals (VSATs), and satellite communications (SATCOM)Military and space

The HMC951A is a compact gallium arsenide (GaAs), monolithic microwave integrated circuit (MMIC), in-phase quadrature (I/Q) downconverter in a RoHS compliant package that operates from 5.6 GHz to 8.6 GHz. This device provides a small signal conversion gain of 13 dB with a noise figure of 2 dB and an image rejection of 32 dBc. The HMC951A uses a low noise amplifier (LNA) followed by an image mixer that is driven by a local oscillator (LO) buffer amplifier. The image reject mixer eliminates the need for a filter following the LNA and removes thermal noise at the image frequency. The IF1 and IF2 mixer outputs are provided and an external 90° hybrid is needed to select the required sideband. The I/Q mixer topology reduces the need for filtering of unwanted sideband. The HMC951A is a smaller alternative to hybrid style, single sideband (SSB) downconverter assemblies, and it eliminates the need for wire bonding by allowing the use of surface-mount manufacturing techniques.The HMC951A is available in 4 mm × 4 mm, 24-lead lead frame chip scale package (LFCSP) and operates over the −40°C to +85°C temperature range. An evaluation board for the HMC951A is also available upon request.ApplicationsPoint to point and point to multipoint radiosMilitary radars, electronic warfare, and electronic intelligenceSatellite communicationsSensors

The HMC952ALP5GE is a four-stage GaAs pHEMT MMIC Medium Power Amplifier with a temperature compensated on-chip power detector which operates between 8 and 14 GHz. The amplifier provides 32 dB of gain and +34.5 dBm of saturated output power at 26% PAE from a +6V supply. With up to +43 dBm IP3 the HMC952ALP5GE is ideal for linear applications such as point-to-point and point-to-multipoint radios or SATCOM applications demanding +34.5dBm of efficient saturated output power. The RF I/Os are internally matched to 50 Ohms.ApplicationsPoint-to-point radiosPoint-to-multi-point radiosSATCO

The HMC953LC4B is a Differential Dual D-Type Flip Flop with a common clock to support data transmission rates of up to 14 Gbps, and selector port operation of up to 14 GHz. During normal operation, dual differential data is transferred to the respective outputs on the positive edge of the clock. Reversing the clock inputs allows for negative-edge triggered applications. The HMC953LC4B also features an output level control pin, VR, which allows for loss compensation or for signal level optimization.All differential input signals to the HMC953LC4B are terminated with 50 Ohms to ground on-chip, and may be either AC or DC coupled. The outputs of the HMC953LC4B may be operated either differentially or single-ended. Outputs can be connected directly to a 50 Ohm terminated system, while DC blocking capacitors may be used if the terminating system is 50 Ohms to a non-ground DC voltage. The HMC- 953LC4B operates from a single -3.3 V DC supply and is available in a ceramic RoHS-compliant 4x4 mm SMT package.Applications16G Fiber ChannelSerial Data Transmission up to 14 GbpsDigital Logic Systems up to 14 GHzMatched Delay ApplicationsBroadband Test & Measurement

The HMC954LC4B is a 2 to 1 Multiplexer designed for 32 Gbps data serialization. The mux latches the two differential inputs on a rising edge of the input clock. The device uses both rising and falling edges of the half-rate clock to serialize the data. The HMC954LC4B also features an output level control pin, VR, which allows for loss compensation or for signal-level optimization.All differential inputs to the HMC954LC4B are CML and terminated on-chip with 50 Ω to the positive supply, GND, and may be AC or DC coupled. The differential CML outputs are source terminated to 50 Ω and may also be AC or DC coupled. Outputs can be connected directly to a 50 Ω ground-terminated system or drive devices with CML logic input. The HMC954LC4B operates from a single −3.3 V supply and is available in a ceramic ROHS-compliant 4 × 4 mm SMT package.APPLICATIONSSONET OC-192Broadband Test & Measurement EquipmentFPGA Interfacing Circuitry16 G and 32 G Fiber Channel100 Gbit Ethernet

The HMC955LC4B is a 1 to 2 Demux designed to support data transmission rates up to 32 Gbps. The demux uses both rising and falling edges of the half-rate clock to sample the data in sequence 01-02 and latches the data on the rising edge into the differential outputs. The demux also has high-speed clock synchronous invert input that allows for scrambling of the data. The HMC955LC4B also features an output level control pin, VR, which allows for loss compensation or for signal level optimization.All differential inputs to the HMC955LC4B are CML and terminated on-chip with 50 Ohms to the positive supply, GND, and may be AC or DC coupled. The differential CML outputs are source terminated to 50 Ohms and may also be AC or DC coupled. Outputs can be connected directly to a 50 Ohm ground-terminated system or drive devices with CML logic input. The HMC955LC4B operates from a single -3.3 V supply and is available in a ceramic ROHS-compliant 4x4 mm SMT package.APPLICATIONSSONET OC-192Broadband Test & Measurement EquipmentFPGA Interfacing Circuitry16 G and 32 G Fiber Channel100 Gbit EthernetADC Encoder

The HMC958LC5 is a 4:1 Selector designed to support data transmission rates of up to 14 Gbps and selector port operation up to 14 GHz. The selector routes the differential inputs to either one or both of the desired outputs upon assertion of the appropriately selected port. The HMC958LC5 also features an output level control pin, VR, which allows for loss compensation or for signal level optimization.All single-ended input signals to the HMC958LC5 are terminated with 50 Ω to ground on-chip, and may be either AC or DC coupled. The outputs of the HMC958LC5 may be operated either differentially or single ended. Outputs can be connected directly to a 50 Ω terminated system, while DC blocking capacitors may be used if the terminating system is 50 Ω to a non-ground DC voltage. The HMC958LC5 operates from a single -3.3V DC supply and is available in a ceramic RoHS compliant 5 × 5 mm SMT package.APPLICATIONSSONET OC-192 and 10 GbE16G Fiber Channel4:1 MultiplexerBuilt-In TestBroadband Test & Measurement

The HMC959LC3 is a Divide-by-4 with Reset designed to support clock frequencies as high as 26 GHz. During normal operation, with the reset pin not asserted, the output toggles from its prior state on the positive edge of the clock. This results in a divide-by-four function of the clock input. Asserting the reset pin forces the Q output low regardless of the clock edge state (asynchronous reset assertion). Reversing the clock inputs allows for negative-edge triggered applications. The HMC959LC3 also features an output level control pin, VR, which allows for loss compensation or for signal level optimization.All input signals to the HMC959LC3 are terminated with 50 Ω to ground on-chip, and may be either AC or DC coupled. Outputs can be connected directly to a 50 Ω terminated system, while DC blocking capacitors may be used if the terminating system is 50 Ω to a non-ground DC voltage. The HMC959LC3 operates from a single -3.3 V DC supply and is available in a ceramic RoHS-compliant 3×3 mm SMT package.APPLICATIONSHigh Speed Frequency Divider (up to 26 GHz)Broadband Test & MeasurementClock SynthesisPhase Locked Loops