| Embedded | 1 | Active | The ADSP-21160N SHARC®DSP is the second iteration of the ADSP-21160. Built in a 0.18 micron CMOS process, it offers higher performance and lower power consumption than its predecessor, the ADSP-21160M. Easing portability, the ADSP-21160N is application source code compatible with first generation ADSP-2106x SHARC DSPs in SISD (Single Instruction, Single Data) mode. To take advantage of the processor’s SIMD (Single Instruction, Multiple Data) capability, some code changes are needed. Like other SHARCs, the ADSP-21160N is a 32-bit processor that is optimized for high performance DSP applications. The ADSP-21160N includes a 100 MHz core, a dual-ported on-chip SRAM, an integrated I/O processor with multiprocessing support, and multiple internal buses to eliminate I/O bottlenecks.The ADSP-21160N introduces Single-Instruction, Multiple-Data (SIMD) processing. Using two computational units (ADSP-2106x SHARC DSPs have one), the ADSP-21160N can double performance versus the ADSP-2106x on a range of DSP algorithms.The ADSP-21160N continues SHARC’s industry-leading standards of integration for DSPs, combining a high-performance 32-bit DSP core with integrated, on-chip system features. These features include a 4M-bit dual ported SRAM memory, host processor interface, I/O processor that supports 14 DMA channels, two serial ports, six link ports, external parallel bus, and glueless multiprocessing. |
| DSP (Digital Signal Processors) | 3 | Active | |
| Integrated Circuits (ICs) | 2 | Active | The ADSP-21161 SHARC®DSP is the newest member of the Super Harvard Architecture (SHARC) family of programmable DSPs. Capable of 600 million math operations per second (MFLOPs), the ADSP-21161 sets a new level of performance for low-cost SHARC DSPs - more than three times the performance for comparable models at about the same price. Its road map includes a cost-effective path to 1200 MFLOPS for $5 per unit and a performance-driven path to 10 GFLOPS and beyond."This newest edition to the SHARC family will open more possibilities for designers to design-in high performance digital signal processing into client-side applications and should help others reconsider applications they couldn’t do before with a single chip," said Will Strauss, president of Forward Concepts. "Analog Devices will certainly maintain customer loyalty with this road map."The ADSP-21161 DSP is the second member of the SHARC DSP family of 32-bit floating-point programmable DSPs to be based on a SIMD core architecture that is optimized for digital signal processing performance. Like all SHARCs, the ADSP-21161 is code-compatible with all other members of the family and supports both fixed- and floating-point data types. The ADSP-21161 lowers the price for SIMD SHARC DSP performance and is an outstanding DSP solution for many price-sensitive applications.State-of-the-Art Development ToolsThe ADSP-21161, like all SHARC processors, is supported by a complete set of software and hardware development tools. The VisualDSP++®tool set offered by Analog Devices includes an optimizing C/C++ compiler, integrated development environment (IDE), assembler, linker, splitter and cycle accurate simulator that support both C and assembly debugging. Emulation support is JTAG-based and ADI offers USB, PCI, and Ethernet based emulators.SHARC DSP RoadmapThere are two code-compatible paths that the SHARC DSP roadmap will follow. One optimized for high-performance multiprocessing systems and the other for price/performance. Performance is the key for multiprocessing applications and this is the reason that ADI will offer 10 GFLOP SHARC DSPs in the future. On-chip memory sizes will be balanced to match this performance with memories increasing to unprecedented levels (64 Mbit) using newly developed technologies.Industry leading price/performance will be the driver on the other path of the roadmap. In the future, these SHARC DSPs will offer an increase in performance to 1200 MFLOPs while decreasing price to as low as $5.00. This is required to support new technologies that demand substantial signal processing performance at consumer price points. |
ADSP-212613rd Generation, Low-Cost, 150 MHz SHARC Processor | Integrated Circuits (ICs) | 3 | Active | The ADSP-21261 is the lowest cost member of the third-generation of SHARC®programmable digital signal processors. A range of cost-sensitive applications such as voice recognition, medical appliances, measurement devices, high-quality audio, and automotive entertainment systems will benefit from the ADSP-21261’s integration of large on-chip memory and diverse set of peripherals.The ADSP-21261 is well suited for use in cost sensitive, signal processing applications.The ADSP-21261 is based on the SHARC (SIMD) core that supports execution of 32-bit fixed-point and 32/40-bit floating-point arithmetic formats. With its core running at 150MHz (6.67 ns instruction cycle time), the ADSP-21261 is capable of executing complex Fast Fourier Transform (FFT) operations—1024-point complex FFT in 61us. The processor’s single-instruction, multiple data (SIMD) mode effectively doubles the processor performance.The ADSP-21261 offers a high level of integration, including 1 Mbit of on-chip dual-ported SRAM and 3Mbits of mask programmable ROM memory. This large on-chip dual-ported memory enables sustained processor and I/O performance without the need for external memory. System I/O is achieved through four full-duplex serial ports, four timers, a 16-bit parallel port, a serial peripheral interface (SPI), 18 zero-overhead Direct Memory Access (DMA) channels delivering fast data transfers without processor intervention and an innovative Digital Audio Interface (DAI) which provides the user complete software control through its Signal Routing Unit (SRU).Digital Audio Interface (DAI) for Simplified I/O System DevelopmentThe ADSP-21261 utilizes the Digital Audio Interface (DAI), an architecture that enables complete software programmability of various on-chip peripherals. The flexibility and ease-of-use of the SHARC programming model, combined with the DAI, allow manufacturers to deploy one hardware configuration into multiple product offerings with different I/O requirements.Connections are made using the flexible Signal Routing Unit (SRU), a matrix routing group of pins that provides configurable and flexible connectivity between all DAI components and the SRU. The peripherals connected through the DAI are: a precision clock generator (PCG), an input data port (IDP), four SPORTS (serial ports), six flag inputs, six flag outputs, three timers and the SRU. The IDP provides an additional input path to the DSP core, configurable as 8 channels of receive serial data or as 7 channels of receive serial data and a single channel of up to a 20-bit wide parallel data. This level of integration enables the designer to take full advantage of a wide variety of peripherals without sacrificing the overall system performance.CROSSCORE Development ToolsAll 3rd Generation SHARC Processors are supported by ADI’s CROSSCORE brand of award winning development tools. The CROSSCORE components include the VisualDSP++™software development environment, EZ-KIT Lite™evaluation systems, and emulators.VisualDSP++ is an integrated software development environment, allowing for fast and easy development, debug, and deployment. The EZ-KIT Lite evaluation system provides an easy way to investigate the power of the ADI family of processors and begin to develop applications. Emulators are available for PCI and USB host platforms for rapid on-chip debugging. Additional development tools and algorithms are available from an extensive third-party development community.Note: The functional block diagram is available in the data sheet. |
ADSP-212623rd Generation Low Cost 32-Bit Floating-Point SHARC DSP | DSP (Digital Signal Processors) | 3 | Active | The ADSP-21262 is the first member of the third-generation of SHARC®programmable DSPs. A range of applications such as high-quality audio and automotive entertainment systems, voice recognition, medical appliances and measurement devices benefit from the ADSP-21262’s integration of large on-chip memory with a wide variety of peripherals—thereby speeding time to market and keeping costs low.The ADSP-21262 is based on the SHARC DSP core that supports execution of 32-bit fixed-point and 32/40-bit floating-point arithmetic formats. With its core running at 200MHz (5 ns instruction cycle time), the ADSP-21262 is capable of executing complex Fast Fourier Transform (FFT) operations—1024-point complex FFT in 46us, more than 2.6x faster than comparatively priced processors. In audio applications, the single-instruction, multiple data (SIMD) mode effectively doubles the processor performance.The ADSP-21262 is designed with the highest level of integration, including 2 Mbit of on-chip dual-ported SRAM and 4 Mbit of mask programmable ROM memory. This large on-chip dual-ported memory enables sustained processor and I/O performance, without the need for external memory. System I/O is achieved through six full-duplex serial ports, four timers, a 16-bit parallel port, a serial peripheral interface (SPI), 22 zero-overhead Direct Memory Access (DMA) channels delivering fast data transfers without processor intervention and an innovative Digital Applications Interface (DAI) offering complete software control through its Signal Routing Unit (SRU).Digital Applications Interface (DAI) for Simplified I/O System DevelopmentThe ADSP-21262 introduces the Digital Applications Interface (DAI), an architecture that enables complete software programmability of various peripherals. The flexibility and ease-of-use of the SHARC programming model, combined with the DAI, allow manufacturers to deploy one hardware configuration into multiple product offerings with different I/O requirements.Connections are made using the flexible Signal Routing Unit (SRU), a matrix routing group of pins that provides configurable and flexible connectivity between all DAI components and the SRU. The peripherals connected through the DAI are: a precision clock generator (PCG), an input data port (IDP), six SPORTS (serial ports), six flag inputs, six flag outputs, three timers and the SRU. The IDP provides an additional input path to the DSP core, configurable as 8 channels of receive serial data or as 7 channels of receive serial data and a single channel of up to a 20-bit wide parallel data. This level of integration enables the designer to take full advantage of a wide variety of peripherals without sacrificing the overall system performance.CROSSCORE Development Tools3rd Generation SHARC DSP members are supported by ADI’s CROSSCORE brand of award winning development tools. The CROSSCORE components include the VisualDSP++™software development environment, EZ-KIT Lite™evaluation systems, and emulators.VisualDSP++ is an integrated software development environment, allowing for fast and easy development, debug, and deployment. The EZ-KIT Lite evaluation system provides an easy way to investigate the power of the ADI family of DSPs and begin to develop applications. Emulators are available for PCI and USB host platforms for rapid on-chip debugging. Additional development tools and algorithms are available from an extensive third-party development community. |
| Embedded | 7 | Active | |
ADSP-21364High Precision 32-Bit Floating-Point SHARC Processor for Professional Audio | Integrated Circuits (ICs) | 5 | Active | The ADSP-2136x SHARC®processor is a member of the SIMD SHARC family of DSPs that feature Analog Devices, Inc., Super Harvard Architecture. The processor is source code-compatible with the ADSP-2126x and ADSP-2116x DSPs, as well as with first generation ADSP-2106x SHARC processors in SISD (single-instruction, single-data) mode. The ADSP-2136x are 32-/40-bit floating-point processors optimized for high performance automotive audio applications. They contain a large on-chip SRAM and ROM, multiple internal buses to eliminate I/O bottlenecks, and an innovative digital audio interface (DAI).As shown in the functional block diagram on Page 1, the ADSP-2136x uses two computational units to deliver a significant performance increase over the previous SHARC processors on a range of signal processing algorithms. With its SIMD computational hardware, the ADSP-2136x can perform two GFLOPS running at 333 MHz. |
| Embedded | 2 | Active | |
ADSP-21369High-Performance 32-bit Floating-Point SHARC Processor for General Purpose Applications | DSP (Digital Signal Processors) | 10 | Active | The third generation of SHARC®Processors offers increased performance, audio and application-focused peripherals, and new memory configurations. The ADSP-21369 increases performance to 400MHz while simplifying algorithm development with the integration of a high-bandwidth and very flexible external memory interface. The ADSP-21369 is based on a single-instruction, multiple-data (SIMD) core which supports both 32-bit fixed-point and 32-/40-bit floating point arithmetic formats and is completely code-compatible with all prior SHARC Processors allowing for maximum reuse of legacy code.The ADSP-21369 increases the amount of on-chip memory to 2Mb SRAM and 6Mb ROM while integrating a variety of audio-specific and general purpose peripherals. Peripherals such as an all digital S/PDIF transmitter/receiver, 8-channel asynchronous sample rate converter, 8 high-speed serial ports, 4 precision clock generators, and multiple serial interfaces combine to ensure the ADSP-21369 maximizes system throughput while minimizing system bill of materials costs. |
| DSP (Digital Signal Processors) | 2 | Active | |
