Analog Devices Inc./Maxim Integrated

The ADSD3500 is a Time-of-Flight (ToF) Depth Image Signal Processor (ISP) for Analog Devices ToF products such as the ADTF3175 and ADSD3030. The Depth ISP processes the raw phase frames from the ToF imager, generating the final radial depth, active brightness (AB), and confidence frames. The ADSD3500 supports full computation of depth, active brightness and confidence data for 640x480 resolution, and partial depth computation (pre-phase unwrap) for 1024x1024 resolution. Data and processing flow is controlled using the integrated ARM®Cortex®-M33. Computation is performed using dedicated hardware and memory, enabling a low power ToF depth ISP solution. The ADSD3500 also controls the boot-up of the image sensor module, loading of calibration data, and triggering of frames.The image data receiver (Rx) and transmitter (Tx) ports use standard Mobile Industry Processor Interface (MIPI) Camera Serial Link 2 (CSI-2) interfaces. Processor programming and operation are controlled through 4-wire QSPI, I2C, and I3C serial interfaces.The ADSD3500 is available in a 3.47mm x 3.47mm WLCSP, and is specified over an operating temperature range of -25°C to +85°C.APPLICATIONSAugmented reality (AR) systemsRoboticsBuilding automationMachine vision systems

TheADSP-21062and ADSP-21060 SHARC DSPs are signal processing microcomputers that offer new capabilities and levels of performance. The ADSP-2106x SHARCs are 32-bit processors optimized for high performance DSP applications. The ADSP-2106x builds on the ADSP-21000 DSP core to form a complete system-on-a-chip, adding a dual-ported on-chip SRAM and integrated I/O peripherals supported by a dedicated I/O bus.Fabricated in a high speed, low power CMOS process, the ADSP-2106x has a 25 ns instruction cycle time and operates at 40 MIPS. With its on-chip instruction cache, the processor can execute every instruction in a single cycle.The ADSP-2106x SHARC DSP represents a new standard of integration for signal computers, combining a high performance floating-point DSP core with integrated, on-chip system features including a 4 Mbit SRAM memory (2 Mbit on the ADSP-21062, 1 Mbit on the ADSP-21061), host processor interface, DMA controller, serial ports, and link port and parallel bus connectivity for glueless DSP multiprocessing.

The ADSP-21065L is a general purpose, programmable 32-bit DSP that allows users to program with equal efficiency in both fixed-point or floating-point arithmetic. This programming flexibility combined with the high performance core and integrated peripherals make the ADSP-21065L an outstanding price/performance value for a broad base of consumer, communications, automotive, industrial and computer applications.The ADSP-21065L is code compatible with ADI's SHARC DSP family and as such customers have immediate access to software and hardware development tools from ADI and SHARC third parties.

The ADSP-21160M DSP is a SHARC processor that is optimized for applications such as telephony, medical imaging, radar/sonar electronics, communications, 3D graphics and imaging. The ADSP-21160M features a Single-Instruction-Multiple-Data (SIMD) architecture.Using two computational units (ALU, Barrel Shifter, MAC, Register files), the ADSP-21160M can have a five fold performance increase versus the ADSP-2106x on a range of DSP algorithms. It is code compatible with ADI's popular first generation ADSP-2106x SHARC DSPs. Like other SHARCs, the ADSP-21160M is a 32-bit processor that is optimized for high performance DSP applications. The ADSP-21160M includes an 80 MHz core for processing both 32-bit fixed-point and (32-bit, 40-bit) floating-point data types, a dual-ported 4 Mbit on-chip SRAM, an integrated I/O processor with multiprocessing support, and multiple internal busses to eliminate I/O bottlenecks.The ADSP-21160M is optimized for multiprocessing topologies; SHARC supports multiprocessing via link ports or an external port. In the diagram below, both cluster and link port multiprocessing is shown. Over the external port up to six 21160Ms may be connected together without any additional support logic. The arbitration for this shared bus is integrated on-chip. Each SHARC in the cluster has access to every SHARC's internal memory. Through the external port connection, optional external memory may be shared as well.The six link ports are another way to gluelessly connect a multiprocessing system. Both, the links and the cluster can be used simultaneously and systems with hundreds of SHARC DSPs can be developed using both peripherals.Maximize Speed, Minimize SizeThe ADSP-21160M is offered in a 27mm x 27mm 400-ball PBGA (Plastic Ball Grid Array) package 40% smaller than processors in this performance class.More Processing Per WattIn addition to small size and high performance, the 21160M's power dissipation enables new levels of MFLOPS per watt. The ADSP-21160M typical power dissipation is 2 watts, enabling 240 MFLOPS of performance per watt. This allows designers to use multiple processors on a PCI card within the PCI power limit of 25 watts. With eight 21160M DSPs, providing 480 MFLOPS each, a standard PCI card design can obtain 3.84 GFLOPS performance and leave 9 watts for other circuitry.The ADSP-21160M is supported by hundreds of readily available third-party hardware and software products and ADI's powerful VisualDSP++ development system, allowing for fast and easy development, debug and deployment.