Analog Devices Inc./Maxim Integrated

The MAX5863 ultra-low-power, highly integrated analog front end is ideal for portable communication equipment such as handsets, PDAs, WLAN, and 3G wireless terminals. The MAX5863 integrates dual 8-bit receive ADCs and dual 10-bit transmit DACs while providing the highest dynamic performance at ultra-low power. The ADCs' analog I-Q input amplifiers are fully differential and accept 1VP-Pfull-scale signals. Typical I-Q channel phase matching is ±0.03° and amplitude matching is ±0.03dB. The ADCs feature 48.5dB SINAD and 69dBc spurious-free dynamic range (SFDR) at fIN= 1.875MHz and fCLK= 7.5Msps. The DACs' analog I-Q outputs are fully differential with ±400mV full-scale output, and 1.4V common-mode level. Typical I-Q channel phase match is ±0.15° and gain match is ±0.05dB. The DACs also feature dual 10-bit resolution with 73dBc SFDR, and 61dB SNR at fOUT= 620kHz and fCLK= 7.5MHz.The ADCs and DACs operate simultaneously or independently for frequency-division duplex (FDD) and time-division duplex (TDD) modes. A 3-wire serial interface controls power-down and transceiver modes of operation. The typical operating power is 22.8mW at fCLK= 7.5Msps with the ADCs and DACs operating simultaneously in transceiver mode. The MAX5863 features an internal 1.024V voltage reference that is stable over the entire operating power-supply range and temperature range. The MAX5863 operates on a +2.7V to +3.3V analog power supply and a +1.8V to +3.3V digital I/O power supply for logic compatibility. The quiescent current is 3.5mA in Idle Mode™ and 1µA in shutdown mode. The MAX5863 is specified for the extended (-40°C to +85°C) temperature range and is available in a 48-pin thin QFN package.See a parametric table of the complete family of pin-compatible AFEs.Applications3G Wireless TerminalsFixed/Mobile Broadband Wireless ModemsNarrowband/Wideband CDMA HandsetsPDAs

The MAX5864 ultra-low-power, highly integrated analog front end is ideal for portable communication equipment such as handsets, PDAs, WLAN, and 3G wireless terminals. The MAX5864 integrates dual 8-bit receive ADCs and dual 10-bit transmit DACs while providing the highest dynamic performance at ultra-low power. The ADCs' analog I-Q input amplifiers are fully differential and accept 1VP-Pfull-scale signals. Typical I-Q channel phase matching is ±0.1° and amplitude matching is ±0.03dB. The ADCs feature 48.5dB SINAD and 69dBc spurious-free dynamic range (SFDR) at fIN= 5.5MHz and fCLK= 22Msps. The DACs' analog I-Q outputs are fully differential with ±400mV full-scale output, and 1.4V common-mode level. Typical I-Q channel phase match is ±0.15° and amplitude match is ±0.05dB. The DACs also feature dual 10-bit resolution with 71.7dBc SFDR, and 57dB SNR at fOUT= 2.2MHz and fCLK= 22MHz.The ADCs and DACs operate simultaneously or independently for frequency-division duplex (FDD) and time-division duplex (TDD) modes. A 3-wire serial interface controls power-down and transceiver modes of operation. The typical operating power is 42mW at fCLK= 22Msps with the ADCs and DACs operating simultaneously in transceiver mode. The MAX5864 features an internal 1.024V voltage reference that is stable over the entire operating power-supply range and temperature range. The MAX5864 operates on a +2.7V to +3.3V analog power supply and a +1.8V to +3.3V digital I/O power supply for logic compatibility. The quiescent current is 5.6mA in idle mode and 1µA in shutdown mode. The MAX5864 is specified for the extended (-40°C to +85°C) temperature range and is available in a 48-pin thin QFN package.Applications3G Wireless TerminalsFixed/Mobile Broadband Wireless ModemsNarrowband/Wideband CDMA HandsetsPDAs

The MAX5865 ultra-low-power, highly integrated analog front end is ideal for portable communication equipment such as handsets, PDAs, WLAN, and 3G wireless terminals. The MAX5865 integrates dual 8-bit receive ADCs and dual 10-bit transmit DACs while providing the highest dynamic performance at ultra-low power. The ADCs' analog I-Q input amplifiers are fully differential and accept 1VP-Pfull-scale signals. Typical I-Q channel phase matching is ±0.2° and amplitude matching is ±0.05dB. The ADCs feature 48.4dB SINAD and 70dBc spurious-free dynamic range (SFDR) at fIN= 5.5MHz and fCLK= 40MHz. The DACs' analog I-Q outputs are fully differential with ±400mV full-scale output, and 1.4V common-mode level. Typical I-Q channel phase matching is ±0.15° and gain matching is ±0.05dB. The DACs also feature dual 10-bit resolution with 72dBc SFDR, and 57dB SNR at fOUT= 2.2MHz and fCLK= 40MHz.The ADCs and DACs operate simultaneously or independently for frequency-division duplex (FDD) and time-division duplex (TDD) modes. A 3-wire serial interface controls power-down and transceiver modes of operation. The typical operating power is 75.6mW at fCLK= 40Msps with the ADCs and DACs operating simultaneously in transceiver mode. The MAX5865 features an internal 1.024V voltage reference that is stable over the entire operating power-supply range and temperature range. The MAX5865 operates on a +2.7V to +3.3V analog power supply and a +1.8V to +3.3V digital I/O power supply for logic compatibility. The quiescent current is 8.5mA in idle mode and 1µA in shutdown mode. The MAX5865 is specified for the extended (-40°C to +85°C) temperature range and is available in a 48-pin thin QFN package.Applications3G Wireless TerminalsFixed/Mobile Broadband Wireless ModemsNarrowband/Wideband CDMA HandsetsPDAs

The MAX5866 ultra-low-power, highly integrated analog front end is ideal for portable communication equipment such as handsets, PDAs, WLAN, and 3G wireless terminals. The MAX5866 integrates dual, 8-bit receive ADCs and dual, 10-bit transmit DACs while providing the highest dynamic performance at ultra-low power. The ADCs' analog I-Q input amplifiers are fully differential and accept 1VP-Pfull-scale signals. Typical I-Q channel phase matching is ±0.2° and amplitude matching is ±0.05dB. The ADCs feature 48dB SINAD and 70.1dBc spurious-free dynamic range (SFDR) at fIN= 25MHz and fCLK= 60MHz. The DACs' analog I-Q outputs are fully differential with ±400mV full-scale output, and 1.4V common-mode level. Typical I-Q channel phase matching is ±0.4° and gain matching is ±0.1dB. The DACs also feature dual, 10-bit resolution with 64.2dBc SFDR, at fOUT= 6MHz and fCLK= 60MHz.The ADCs and DACs operate simultaneously or independently for frequency-division duplex (FDD) and time-division duplex (TDD) modes. A 3-wire serial interface controls power-down and transceiver modes of operation. The typical operating power is 96mW at fCLK= 60MHz with the ADCs and DACs operating simultaneously in transceiver mode. The MAX5866 features an internal 1.024V voltage reference that is stable over the entire operating power-supply range and temperature range. The MAX5866 operates on a +2.7V to +3.3V analog power supply and a +2.7V to +3.3V digital I/O power supply for logic compatibility. The quiescent current is 12mA in idle mode and 1µA in shutdown mode. The MAX5866 is specified for the extended (-40°C to +85°C) temperature range and is available in a 48-pin thin QFN package.Applications3G Wireless TerminalsFixed/Mobile Broadband Wireless ModemsNarrowband/Wideband CDMA Handsets and PDAsVSAT Modems

The MAX5869 high-performance interpolating and modulating 16-bit 5.9Gsps RF DAC can directly synthesize up to 600MHz of instantaneous bandwidth from DC to frequencies greater than 2.8GHz. The device is optimized for digital video broadcast and cable applications and meets spectral mask requirements for a broad set of communication standards including DVB-T, DVB-T2, DVB-C2, DVB-S2, DVB-S2X, ISDB-T, EPoC, and DOCSIS 3.0/3.1.The device integrates interpolation filters, a digital quadrature modulator, a numerically controlled oscillator (NCO), clock multiplying PLL+VCO and a 14-bit RF DAC core. The user-configurable 5x, 6x, 6.67x, 8x, 10x, 12x, 13.33x, 16x, 20x or 24x, linear phase interpolation filters simplify reconstruction filtering, while enhancing passband dynamic performance, and reduce the input data bandwidth required from an FPGA/ASIC. The NCO allows for fully agile modulation of the input baseband signal for direct RF synthesis.The MAX5869 accepts 16-bit input data via a four-lane JESD204B SerDes data input interface that is Subclass-0 and Subclass-1 compliant. The interface can be configured for 1, 2, or 4 lanes and supports data rates up to 10Gbps per lane allowing flexibility to optimize the I/O count and speed.The MAX5869 clock input has a flexible clock interface and accepts a differential sine-wave, or square-wave input clock signal. A bypassable clock multiplying PLL and VCO can be used to generate a high-frequency sampling clock. The device outputs a divided reference clock to ensure synchronization of the system clock and DAC clock. In addition, multiple devices can be synchronized using JESD204B Subclass-1.The MAX5869 uses a differential current-steering architecture and can produce a 0dBm full-scale output signal level with a 50Ω load. Operating from 1.8V and 1.0V power supplies, the device consumes 2.5W at 4.9Gsps. The device is offered in a compact 144-pin, 10mm x 10mm, FCCSP package and is specified for the extended industrial temperature range (-40°C to +85°C).ApplicationsDigital Video Broadcast:DVB-T/DVB-T2/ISDB-T Modulators,DVB-C2/DVB-S2/DVB-S2X ModulatorsDownstream DOCSIS CMTS ModulatorsEthernet PON over Coax (EPoC)

The MAX5871 high-performance interpolating and modulating 16-bit 5.9Gsps RF DAC can directly synthesize up to 600MHz of instantaneous bandwidth from DC to frequencies greater than 2.8GHz. The device enables multi-standard and multi-band transmitters in wireless communications applications. The device meets spectral mask requirements for a broad set of communication standards including multicarrier GSM, UMTS, and LTE.The device integrates interpolation filters, a digital quadrature modulator, a numerically controlled oscillator (NCO), clock multiplying PLL+VCO and a 14-bit RF DAC core. The user-configurable 5x, 6x, 6.67x, 8x, 10x, 12x, 13.33x, 16x, 20x or 24x, linear phase interpolation filters simplify reconstruction filtering, while enhancing passband dynamic performance, and reduce the input data bandwidth required from an FPGA/ASIC. The NCO allows for fully agile modulation of the input baseband signal for direct RF synthesis.The MAX5871 accepts 16-bit input data via a four-lane JESD204B SerDes data input interface that is Subclass-0 and Subclass-1 compliant. The interface can be configured for 1, 2, or 4 lanes and supports data rates up to 10Gbps per lane allowing flexibility to optimize the I/O count and speed.The MAX5871 clock input has a flexible clock interface and accepts a differential sine-wave, or square-wave input clock signal. A bypassable clock multiplying PLL and VCO can be used to generate a high-frequency sampling clock. The device outputs a divided reference clock to ensure synchronization of the system clock and DAC clock. In addition, multiple devices can be synchronized using JESD204B Subclass-1.The MAX5871 uses a differential current-steering architecture and can produce a 0dBm full-scale output signal level with a 50Ω load. Operating from 1.8V and 1.0V power supplies, the device consumes 2.5W at 4.9Gsps. The device is offered in a compact 144-pin, 10mm x 10mm, FCCSP package and is specified for the extended industrial temperature range (-40°C to +85°C).ApplicationsCellular Base-Station Transmitters2.5G/3G - GSM/TDMA/CDMA/UMTS4G LTE and WiMAXMulti-Standard and Multi-Band TransmittersPoint-to-Point Microwave LinksWireless Backhaul

The MAX5874 is an advanced 14-bit, 200Msps, dual digital-to-analog converter (DAC). This DAC meets the demanding performance requirements of signal synthesis applications found in wireless base stations and other communications applications. Operating from 3.3V and 1.8V supplies, this dual DAC offers exceptional dynamic performance such as 78dBc spurious-free dynamic range (SFDR) at fOUT= 16MHz and supports update rates of 200Msps, with a power dissipation of only 260mW.The MAX5874 utilizes a current-steering architecture that supports a 2mA to 20mA full-scale output current range, and allows a 0.1VP-Pto 1VP-Pdifferential output voltage swing. The device features an integrated 1.2V bandgap reference and control amplifier to ensure high-accuracy and low-noise performance. A separate reference input (REFIO) allows for the use of an external reference source for optimum flexibility and improved gain accuracy.The digital and clock inputs of the MAX5874 accept 3.3V CMOS voltage levels. The device features a flexible input data bus that allows for dual-port input or a single-interleaved data port. The MAX5874 is available in a 68-pin QFN package with an exposed paddle (EP) and is specified for the extended temperature range (-40°C to +85°C).Refer to theMAX5873andMAX5875data sheets for pin-compatible 12-bit and 16-bit versions of the MAX5874, respectively. Refer to theMAX5877for an LVDS-compatible version of the MAX5874.See a parametric table of the complete family of pin-compatible 12-/14-/16-bit high-speed DACs.ApplicationsAutomated Test Equipment (ATE)Base Stations: Single-/Multicarrier UMTS, CDMA, GSMCable Modem Termination Systems (CMTS)Communications: Fixed Broadband Wireless Access, Point-to-Point MicrowaveDirect Digital Synthesis (DDS)Instrumentation