SN74AUP1G80 Series

Low-Power Single Postitive-Edge-Triggered D-Type Flip-Flop

Catalog

Low-Power Single Postitive-Edge-Triggered D-Type Flip-Flop

Part	Function	Number of Bits per Element	Type	Clock Frequency	Supplier Device Package	Mounting Type	Voltage - Supply [Min]	Voltage - Supply [Max]	Max Propagation Delay @ V, Max CL	Number of Elements	Output Type	Input Capacitance	Operating Temperature [Max]	Operating Temperature [Min]	Trigger Type	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Package / Case
Texas Instruments SN74AUP1G80DBVTG4	Standard	1	D-Type	260 MHz	SOT-23-5	Surface Mount	0.8 V	3.6 V	6.4 ns	1	1.81 mOhm	1.5 pF	85 °C	-40 °C	Positive Edge	4 mA	4 mA	SC-74A SOT-753
Texas Instruments SN74AUP1G80DBVT	Standard	1	D-Type	260 MHz	SOT-23-5	Surface Mount	0.8 V	3.6 V	6.4 ns	1	1.81 mOhm	1.5 pF	85 °C	-40 °C	Positive Edge	4 mA	4 mA	SC-74A SOT-753
Texas Instruments SN74AUP1G80DSFR	Standard	1	D-Type	260 MHz	6-SON (1x1)	Surface Mount	0.8 V	3.6 V	6.4 ns	1	1.81 mOhm	1.5 pF	85 °C	-40 °C	Positive Edge	4 mA	4 mA	6-XFDFN
Texas Instruments SN74AUP1G80DCKT	Standard	1	D-Type	260 MHz	SC-70-5	Surface Mount	0.8 V	3.6 V	6.4 ns	1	1.81 mOhm	1.5 pF	85 °C	-40 °C	Positive Edge	4 mA	4 mA	5-TSSOP SC-70-5 SOT-353
Texas Instruments SN74AUP1G80DPWR	Standard	1	D-Type	260 MHz	5-X2SON (0.8x0.8)	Surface Mount	0.8 V	3.6 V	6.4 ns	1	1.81 mOhm	1.5 pF	85 °C	-40 °C	Positive Edge	4 mA	4 mA	4-XFDFN Exposed Pad
Texas Instruments SN74AUP1G80DRYR	Standard	1	D-Type	260 MHz	6-SON (1.45x1)	Surface Mount	0.8 V	3.6 V	6.4 ns	1	1.81 mOhm	1.5 pF	85 °C	-40 °C	Positive Edge	4 mA	4 mA	6-UFDFN
Texas Instruments SN74AUP1G80DBVRG4	Standard	1	D-Type	260 MHz	SOT-23-5	Surface Mount	0.8 V	3.6 V	6.4 ns	1	1.81 mOhm	1.5 pF	85 °C	-40 °C	Positive Edge	4 mA	4 mA	SC-74A SOT-753
Texas Instruments SN74AUP1G80DCKTG4	Standard	1	D-Type	260 MHz	SC-70-5	Surface Mount	0.8 V	3.6 V	6.4 ns	1	1.81 mOhm	1.5 pF	85 °C	-40 °C	Positive Edge	4 mA	4 mA	5-TSSOP SC-70-5 SOT-353
Texas Instruments SN74AUP1G80DCKR	Standard	1	D-Type	260 MHz	SC-70-5	Surface Mount	0.8 V	3.6 V	6.4 ns	1	1.81 mOhm	1.5 pF	85 °C	-40 °C	Positive Edge	4 mA	4 mA	5-TSSOP SC-70-5 SOT-353

Catalog

Low-Power Single Postitive-Edge-Triggered D-Type Flip-Flop

Key Features

• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Performance Tested Per JESD 222000-V Human-Body Model(A114-B, Class II)1000-V Charged-Device Model (C101)Available in the Texas Instruments NanoStar™ PackageLow Static-Power Consumption(ICC= 0.9 µA Maximum)Low Dynamic-Power Consumption(Cpd= 4.3 pF Typical at 3.3 V)Low Input Capacitance (Ci= 1.5 pF Typical)Low Noise – Overshoot and Undershoot <10% of VCCIoffSupports Partial-Power-Down Mode OperationSchmitt-Trigger Action Allows Slow Input Transition and Better Switching Noise Immunity at the Input(Vhys= 250 mV Typical at 3.3 V)Wide Operating VCCRange of 0.8 V to 3.6 VOptimized for 3.3-V Operation3.6-V I/O Tolerant to Support Mixed-Mode Signal Operationtpd= 4.4 ns Maximum at 3.3 VSuitable for Point-to-Point ApplicationsLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Performance Tested Per JESD 222000-V Human-Body Model(A114-B, Class II)1000-V Charged-Device Model (C101)Available in the Texas Instruments NanoStar™ PackageLow Static-Power Consumption(ICC= 0.9 µA Maximum)Low Dynamic-Power Consumption(Cpd= 4.3 pF Typical at 3.3 V)Low Input Capacitance (Ci= 1.5 pF Typical)Low Noise – Overshoot and Undershoot <10% of VCCIoffSupports Partial-Power-Down Mode OperationSchmitt-Trigger Action Allows Slow Input Transition and Better Switching Noise Immunity at the Input(Vhys= 250 mV Typical at 3.3 V)Wide Operating VCCRange of 0.8 V to 3.6 VOptimized for 3.3-V Operation3.6-V I/O Tolerant to Support Mixed-Mode Signal Operationtpd= 4.4 ns Maximum at 3.3 VSuitable for Point-to-Point Applications

Description

The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family assures a low static- and dynamic-power consumption across the entire VCCrange of 0.8 V to 3.6 V, resulting in increased battery life (seeAUP – The Lowest-Power Family). This product also maintains excellent signal integrity (seeExcellent Signal Integrity). This is a single positive-edge-triggered D-type flip-flop. When data at the data (D) input meets the setup time requirement, the data is transferred to theQoutput on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device. The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family assures a low static- and dynamic-power consumption across the entire VCCrange of 0.8 V to 3.6 V, resulting in increased battery life (seeAUP – The Lowest-Power Family). This product also maintains excellent signal integrity (seeExcellent Signal Integrity). This is a single positive-edge-triggered D-type flip-flop. When data at the data (D) input meets the setup time requirement, the data is transferred to theQoutput on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.