CY74FCT2573TSOCT
ActiveOCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS AND SERIES DAMPING RESISTORS
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CY74FCT2573TSOCT
ActiveOCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS AND SERIES DAMPING RESISTORS
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Technical Specifications
Parameters and characteristics for this part
| Specification | CY74FCT2573TSOCT |
|---|---|
| Circuit [custom] | 8 |
| Circuit [custom] | 8 |
| Current - Output High, Low [custom] | 15 mA |
| Current - Output High, Low [custom] | 12 mA |
| Independent Circuits | 1 |
| Logic Type | D-Type Transparent Latch |
| Mounting Type | Surface Mount |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Tri-State |
| Package / Case | 20-SOIC |
| Package / Case [y] | 0.295 in |
| Package / Case [y] | 7.5 mm |
| Supplier Device Package | 20-SOIC |
| Voltage - Supply [Max] | 5.25 V |
| Voltage - Supply [Min] | 4.75 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 1.14 | |
| Digi-Reel® | 1 | $ 1.14 | ||
| Tape & Reel (TR) | 2000 | $ 0.48 | ||
| 6000 | $ 0.46 | |||
| 10000 | $ 0.44 | |||
| Texas Instruments | LARGE T&R | 1 | $ 0.84 | |
| 100 | $ 0.65 | |||
| 250 | $ 0.48 | |||
| 1000 | $ 0.34 | |||
Description
General part information
CY74FCT2573T Series
The CY74FCT2573T is an 8-bit, high-speed CMOS, TTL-compatible buffered latch with 3-state outputs that is ideal for driving high-capacitance loads, such as memory and address buffers. On-chip 25-termination resistors at the outputs reduce system noise caused by reflections. The CY74FCT2573T can replace the CY74FCT573T to reduce noise in an existing design.
When the latch-enable (LE) input is high, the flip-flops appear transparent to the data. Data that meets the required setup times are latched when LE transitions from high to low. Data appears on the bus when the output-enable (OE\) input is low. When OE\ is high, the bus output is in the high-impedance state. In this mode, data can be entered into the latches.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Documents
Technical documentation and resources
