CY74FCT2573T Series

Octal D-Type Transparent Latches with 3-State Outputs and Series Damping Resistors

Catalog

Octal D-Type Transparent Latches with 3-State Outputs and Series Damping Resistors

Part	Output Type	Circuit [custom]	Circuit [custom]	Independent Circuits	Package / Case	Package / Case [y]	Package / Case [y]	Mounting Type	Voltage - Supply [Min]	Voltage - Supply [Max]	Supplier Device Package	Logic Type	Operating Temperature [Max]	Operating Temperature [Min]	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Package / Case [custom]	Package / Case [custom]
Texas Instruments CY74FCT2573TSOCT	Tri-State	8	8	1	20-SOIC	0.295 in	7.5 mm	Surface Mount	4.75 V	5.25 V	20-SOIC	D-Type Transparent Latch	85 °C	-40 °C	15 mA	12 mA
Texas Instruments CY74FCT2573CTQC
Texas Instruments CY74FCT2573CTQCT	Tri-State	8	8	1	20-SSOP			Surface Mount	4.75 V	5.25 V	20-SSOP	D-Type Transparent Latch	85 °C	-40 °C	15 mA	12 mA	0.154 in	3.9 mm
Texas Instruments CY74FCT2573CTSOCG4	Tri-State	8	8	1	20-SOIC	0.295 in	7.5 mm	Surface Mount	4.75 V	5.25 V	20-SOIC	D-Type Transparent Latch	85 °C	-40 °C	15 mA	24 mA
Texas Instruments CY74FCT2573CTSOC	Tri-State	8	8	1	20-SOIC	0.295 in	7.5 mm	Surface Mount	4.75 V	5.25 V	20-SOIC	D-Type Transparent Latch	85 °C	-40 °C	15 mA	12 mA
Texas Instruments CY74FCT2573ATQCT	Tri-State	8	8	1	20-SSOP			Surface Mount	4.75 V	5.25 V	20-SSOP	D-Type Transparent Latch	85 °C	-40 °C	15 mA	12 mA	0.154 in	3.9 mm
Texas Instruments CY74FCT2573ATQCTG4	Tri-State	8	8	1	20-SSOP			Surface Mount	4.75 V	5.25 V	20-SSOP/QSOP	D-Type Transparent Latch	85 °C	-40 °C	15 mA	12 mA	0.154 in	3.9 mm

Catalog

Octal D-Type Transparent Latches with 3-State Outputs and Series Damping Resistors

Key Features

• Function and Pinout Compatible With the Fastest Bipolar Logic25-Output Series Resistors Reduce Transmission-Line Reflection NoiseReduced VOH(Typically = 3.3 V) Version of Equivalent FCT FunctionsEdge-Rate Control Circuitry for Significantly Improved Noise CharacteristicsIoffSupports Partial-Power-Down Mode OperationMatched Rise and Fall Times3-State OutputsESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)Fully Compatible With TTL Input and Output Logic Levels12-mA Output Sink Current15-mA Output Source CurrentFunction and Pinout Compatible With the Fastest Bipolar Logic25-Output Series Resistors Reduce Transmission-Line Reflection NoiseReduced VOH(Typically = 3.3 V) Version of Equivalent FCT FunctionsEdge-Rate Control Circuitry for Significantly Improved Noise CharacteristicsIoffSupports Partial-Power-Down Mode OperationMatched Rise and Fall Times3-State OutputsESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)Fully Compatible With TTL Input and Output Logic Levels12-mA Output Sink Current15-mA Output Source Current

Description

The CY74FCT2573T is an 8-bit, high-speed CMOS, TTL-compatible buffered latch with 3-state outputs that is ideal for driving high-capacitance loads, such as memory and address buffers. On-chip 25-termination resistors at the outputs reduce system noise caused by reflections. The CY74FCT2573T can replace the CY74FCT573T to reduce noise in an existing design. When the latch-enable (LE) input is high, the flip-flops appear transparent to the data. Data that meets the required setup times are latched when LE transitions from high to low. Data appears on the bus when the output-enable (OE\) input is low. When OE\ is high, the bus output is in the high-impedance state. In this mode, data can be entered into the latches. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The CY74FCT2573T is an 8-bit, high-speed CMOS, TTL-compatible buffered latch with 3-state outputs that is ideal for driving high-capacitance loads, such as memory and address buffers. On-chip 25-termination resistors at the outputs reduce system noise caused by reflections. The CY74FCT2573T can replace the CY74FCT573T to reduce noise in an existing design. When the latch-enable (LE) input is high, the flip-flops appear transparent to the data. Data that meets the required setup times are latched when LE transitions from high to low. Data appears on the bus when the output-enable (OE\) input is low. When OE\ is high, the bus output is in the high-impedance state. In this mode, data can be entered into the latches. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.