
TL16C550DRHBR
ActiveASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL
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TL16C550DRHBR
ActiveASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL
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Technical Specifications
Parameters and characteristics for this part
| Specification | TL16C550DRHBR |
|---|---|
| Data Rate (Max) | 1 Mbps |
| FIFO's | 16 Byte |
| Mounting Type | Surface Mount |
| Number of Channels [custom] | UART |
| Number of Channels [custom] | 1 |
| Package / Case | 32-VFQFN Exposed Pad |
| Supplier Device Package | 32-VQFN (5x5) |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 2.25 V |
| With Auto Flow Control | True |
| With False Start Bit Detection | True |
| With Modem Control | True |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tape & Reel (TR) | 3000 | $ 1.94 | |
| Texas Instruments | LARGE T&R | 1 | $ 2.91 | |
| 100 | $ 2.55 | |||
| 250 | $ 1.79 | |||
| 1000 | $ 1.44 | |||
Description
General part information
TL16C550D Series
The TL16C550D and the TL16C550DI are speed and operating voltage upgrades (but functional equivalents) of the TL16C550C asynchronous communications element (ACE), which in turn is a functional upgrade of the TL16C450. Functionally equivalent to the TL16C450 on power up (character or TL16C450 mode), the TL16C550D and the TL16C550DI, like the TL16C550C, can be placed in an alternate FIFO mode. This relieves the CPU of excessive software overhead by buffering received and transmitted characters. The receiver and transmitter FIFOs store up to 16 bytes including three additional bits of error status per byte for the receiver FIFO. In the FIFO mode, there is a selectable autoflow control feature that can significantly reduce software overload and increase system efficiency by automatically controlling serial data flow usingRTSoutput andCTSinput signals.
The TL16C550D and TL16C550DI perform serial-to-parallel conversions on data received from a peripheral device or modem and parallel-to-serial conversion on data received from its CPU. The CPU can read the ACE status at any time. The ACE includes complete modem control capability and a processor interrupt system that can be tailored to minimize software management of the communications link.
Both the TL16C550D and the TL16C550DI ACE include a programmable baud rate generator capable of dividing a reference clock by divisors from 1 to 65535 and producing a 16× reference clock for the internal transmitter logic. Provisions are included to use this 16× clock for the receiver logic. The ACE accommodates up to a 1.5-Mbaud serial rate (24-MHz input clock) so that a bit time is 667 ns and a typical character time is 6.7 ms (start bit, 8 data bits, stop bit).
Documents
Technical documentation and resources