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Technical Specifications
Parameters and characteristics for this part
| Specification | AD5317ARU-REEL7 |
|---|---|
| Architecture | String DAC |
| Data Interface | DSP, SPI |
| Differential Output | False |
| INL/DNL (LSB) | 0.5 LSB, 0.05 LSB |
| Mounting Type | Surface Mount |
| Number of Bits [custom] | 10 |
| Number of D/A Converters | 4 |
| Operating Temperature [Max] | 105 ░C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Voltage - Buffered |
| Package / Case | 16-TSSOP |
| Package / Case [x] | 0.173 in |
| Package / Case [y] | 4.4 mm |
| Reference Type | External |
| Settling Time | 9 µs |
| Supplier Device Package | 16-TSSOP |
| Voltage - Supply, Analog [Max] | 5.5 V |
| Voltage - Supply, Analog [Min] | 2.5 V |
| Voltage - Supply, Digital [Max] | 5.5 V |
| Voltage - Supply, Digital [Min] | 2.5 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
Description
General part information
AD5317R Series
The AD5317R, a member of thenanoDAC®family, is a low power, quad, 10-bit buffered voltage output DAC. The device includes a 2.5 V, 2 ppm/°C internal reference (enabled by default) and a gain select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). The device operates from a single 2.7 V to 5.5 V supply, is guaranteed monotonic by design, and exhibits less than 0.1% FSR gain error and 1.5 mV offset error performance. The device is available in a 3 mm × 3 mm LFCSP and a TSSOP package.The AD5317R also incorporates a power-on reset circuit and a RSTSEL pin that ensures that the DAC outputs power up to zero scale or midscale and remain at that level until a valid write takes place. Each part contains a per-channel power-down feature that reduces the current consumption of the device to 4 µA at 3 V while in power-down mode.The AD5317R employs a versatile SPI interface that operates at clock rates up to 50 MHz and contains a VLOGICpin intended for 1.8 V/3 V/5 V logic.Product HighlightsPrecision DC Performance. Total unadjusted error: ±0.1% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.1% of FSR maximumLow Drift 2.5 V On-Chip Reference. 2 ppm/°C typical temperature coefficient 5 ppm/°C maximum temperature coefficientTwo Package Options. 3 mm × 3 mm, 16-lead LFCSP 16-lead TSSOPApplicationsDigital gain and offset adjustmentProgrammable attenuatorsIndustrial automationData acquisition systems
Documents
Technical documentation and resources