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16 SOIC
Integrated Circuits (ICs)

CD4042BD

Obsolete
Texas Instruments

IC QUAD CLOCKED D LATCH 16SOIC

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Search across all available documentation for this part.

DocumentsLogic Guide (Rev. AB)Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)+6
16 SOIC
Integrated Circuits (ICs)

CD4042BD

Obsolete
Texas Instruments

IC QUAD CLOCKED D LATCH 16SOIC

Deep-Dive with AI

DocumentsLogic Guide (Rev. AB)Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)+6

Technical Specifications

Parameters and characteristics for this part

SpecificationCD4042BD
Circuit1:1
Current - Output High, Low [custom]6.8 mA
Current - Output High, Low [custom]6.8 mA
Independent Circuits4
Logic TypeD-Type Transparent Latch
Mounting TypeSurface Mount
Operating Temperature [Max]125 °C
Operating Temperature [Min]-55 °C
Output TypeDifferential
Package / Case16-SOIC
Package / Case [x]0.154 in
Package / Case [y]3.9 mm
Supplier Device Package16-SOIC
Voltage - Supply [Max]18 V
Voltage - Supply [Min]3 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTube 1$ 1.13
Texas InstrumentsTUBE 1$ 0.84
100$ 0.64
250$ 0.47
1000$ 0.34

Description

General part information

CD4042B Series

CD4042B types contain four latch circuits, each strobed by a common clock. Complementary buffered outputs are available from each circuit. The impedance of the n- and p-channel output devices is balanced and all outputs are electrically identical.

Information present at the data input is transferred to outputs Q and Q\ during the CLOCK level which is programmed by the POLARITY input. For POLARITY = 0 the transfer occurs during the 0 CLOCK level and for POLARITY = 1 the transfer occurs during the 1 CLOCK level. The outputs follow the data input providing the CLOCK and POLARITY levels defined above are present. When a CLOCK transition occurs (positive for POLARITY = 0 and negative for POLARITY = 1) the information present at the input during the CLOCK transition is retained at the output until an opposite CLOCK transition occurs.

The CD4042B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffixes), 16-lead dual-in-line plastic package (E suffix), 16-lead small-outline packages (D, DR, DT, DW, DWR, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).