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Technical Specifications
Parameters and characteristics for this part
| Specification | CD4042BDWR |
|---|---|
| Circuit | 1:1 |
| Current - Output High, Low [custom] | 6.8 mA |
| Current - Output High, Low [custom] | 6.8 mA |
| Independent Circuits | 4 |
| Logic Type | D-Type Transparent Latch |
| Mounting Type | Surface Mount |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -55 °C |
| Output Type | Differential |
| Package / Case | 16-SOIC |
| Package / Case [x] | 0.295 in |
| Package / Case [y] | 7.5 mm |
| Supplier Device Package | 16-SOIC |
| Voltage - Supply [Max] | 18 V |
| Voltage - Supply [Min] | 3 V |
CD4042B Series
CMOS Quad Clocked 'D' Latch
| Part | Current - Output High, Low [custom] | Current - Output High, Low [custom] | Independent Circuits | Operating Temperature [Min] | Operating Temperature [Max] | Voltage - Supply [Max] | Voltage - Supply [Min] | Logic Type | Mounting Type | Circuit | Supplier Device Package | Package / Case [x] | Package / Case | Package / Case [y] | Output Type | Package / Case | Package / Case |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments | 6.8 mA | 6.8 mA | 4 | -55 °C | 125 °C | 18 V | 3 V | D-Type Transparent Latch | Surface Mount | 1:1 | 16-SOIC | 0.295 in | 16-SOIC | 7.5 mm | Differential | ||
 Texas Instruments | 6.8 mA | 6.8 mA | 4 | -55 °C | 125 °C | 18 V | 3 V | D-Type Transparent Latch | Surface Mount | 1:1 | 16-SOIC | 0.295 in | 16-SOIC | 7.5 mm | Differential | ||
 Texas Instruments | 6.8 mA | 6.8 mA | 4 | -55 °C | 125 °C | 18 V | 3 V | D-Type Transparent Latch | Through Hole | 1:1 | 16-PDIP | 16-DIP | Differential | 0.3 in | 7.62 mm | ||
 Texas Instruments | 6.8 mA | 6.8 mA | 4 | -55 °C | 125 °C | 18 V | 3 V | D-Type Transparent Latch | Surface Mount | 1:1 | 16-SOIC | 0.154 in | 16-SOIC | 3.9 mm | Differential | ||
 Texas Instruments | 6.8 mA | 6.8 mA | 4 | -55 °C | 125 °C | 18 V | 3 V | D-Type Transparent Latch | Surface Mount | 1:1 | 16-TSSOP | 0.173 in | 16-TSSOP | 4.4 mm | Differential | ||
Texas Instruments | 6.8 mA | 6.8 mA | 4 | -55 °C | 125 °C | 18 V | 3 V | D-Type Transparent Latch | Surface Mount | 1:1 | 16-SOIC | 0.295 in | 16-SOIC | 7.5 mm | Differential | ||
Texas Instruments | 6.8 mA | 6.8 mA | 4 | -55 °C | 125 °C | 18 V | 3 V | D-Type Transparent Latch | Surface Mount | 1:1 | 16-SOIC | 0.154 in | 16-SOIC | 3.9 mm | Differential | ||
Texas Instruments | 6.8 mA | 6.8 mA | 4 | -55 °C | 125 °C | 18 V | 3 V | D-Type Transparent Latch | Through Hole | 1:1 | 16-PDIP | 16-DIP | Differential | 0.3 in | 7.62 mm | ||
 Texas Instruments | 6.8 mA | 6.8 mA | 4 | -55 °C | 125 °C | 18 V | 3 V | D-Type Transparent Latch | Surface Mount | 1:1 | 16-TSSOP | 0.173 in | 16-TSSOP | 4.4 mm | Differential | ||
 Texas Instruments | 6.8 mA | 6.8 mA | 4 | -55 °C | 125 °C | 18 V | 3 V | D-Type Transparent Latch | Surface Mount | 1:1 | 16-SO | 16-SOIC | Differential | 0.209 " | 5.3 mm |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
Description
General part information
CD4042B Series
CD4042B types contain four latch circuits, each strobed by a common clock. Complementary buffered outputs are available from each circuit. The impedance of the n- and p-channel output devices is balanced and all outputs are electrically identical.
Information present at the data input is transferred to outputs Q and Q\ during the CLOCK level which is programmed by the POLARITY input. For POLARITY = 0 the transfer occurs during the 0 CLOCK level and for POLARITY = 1 the transfer occurs during the 1 CLOCK level. The outputs follow the data input providing the CLOCK and POLARITY levels defined above are present. When a CLOCK transition occurs (positive for POLARITY = 0 and negative for POLARITY = 1) the information present at the input during the CLOCK transition is retained at the output until an opposite CLOCK transition occurs.
The CD4042B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffixes), 16-lead dual-in-line plastic package (E suffix), 16-lead small-outline packages (D, DR, DT, DW, DWR, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
Documents
Technical documentation and resources