Integrated Circuits (ICs)

CDC2510PWR

NRND

Texas Instruments

CLOCK GENERATOR 1CLOCK INPUTS 24-PIN TSSOP T/R

Deep-Dive with AI

Search across all available documentation for this part.

Integrated Circuits (ICs)

CDC2510PWR

NRND

Texas Instruments

CLOCK GENERATOR 1CLOCK INPUTS 24-PIN TSSOP T/R

Deep-Dive with AI

Specifications Series Pricing Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	CDC2510PWR

Differential - Input:Output	False
Divider/Multiplier	False
Frequency - Max [Max]	125 MHz
Input	Clock
Mounting Type	Surface Mount
Number of Circuits	1
Operating Temperature [Max]	70 °C
Operating Temperature [Min]	0 °C
Output	Clock
Package / Case	24-TSSOP
Package / Case	0.173 in, 4.4 mm
PLL	Yes with Bypass
Ratio - Input:Output [custom]	1:10
Supplier Device Package	24-TSSOP
Type	PLL Clock Driver
Voltage - Supply [Max]	3.6 V
Voltage - Supply [Min]	3 V

CDC2510C Series

3.3-V PLL clock driver with support for PC SDRAM registered DIMM design support document rev. 1.2

Part	Mounting Type	Number of Circuits	Supplier Device Package	Ratio - Input:Output [custom]	Package / Case	Package / Case	Type	Input	Operating Temperature [Max]	Frequency - Max [Max]	Output	Voltage - Supply [Max]	Voltage - Supply [Min]	PLL
Texas Instruments CDC2510CPWG4	Surface Mount	1	24-TSSOP	1:10	24-TSSOP	0.173 in 4.4 mm	PLL Clock Driver	Clock	85 °C	125 MHz	Clock	3.6 V	3 V	Yes with Bypass
Texas Instruments CDC2510CPW	Surface Mount	1	24-TSSOP	1:10	24-TSSOP	0.173 in 4.4 mm	PLL Clock Driver	Clock	85 °C	125 MHz	Clock	3.6 V	3 V	Yes with Bypass
Texas Instruments CDC2510PWR	Surface Mount	1	24-TSSOP	1:10	24-TSSOP	0.173 in 4.4 mm	PLL Clock Driver	Clock	70 °C	125 MHz	Clock	3.6 V	3 V	Yes with Bypass
Texas Instruments CDC2510APWR	Surface Mount	1	24-TSSOP	1:10	24-TSSOP	0.173 in 4.4 mm	PLL Clock Driver	Clock	70 °C		Clock	3.6 V	3 V	Yes with Bypass
Texas Instruments CDC2510BPWR	Surface Mount	1	24-TSSOP	1:10	24-TSSOP	0.173 in 4.4 mm	PLL Clock Driver	Clock	70 °C	125 MHz	Clock	3.6 V	3 V	Yes with Bypass

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tape & Reel (TR)	2000	$ 8.76

Description

General part information

CDC2510C Series

The CDC2510C is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC2510C operates at VCC= 3.3 V . It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.

One bank of ten outputs provides ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to the logic-low state.

Unlike many products containing PLLs, the CDC2510C does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.

Documents

Technical documentation and resources

No documents available