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64-QFN
Integrated Circuits (ICs)

ADS42JB69IRGCR

Active
Texas Instruments

DUAL-CHANNEL, 16-BIT, 250-MSPS ANALOG-TO-DIGITAL CONVERTER (ADC)

64-QFN
Integrated Circuits (ICs)

ADS42JB69IRGCR

Active
Texas Instruments

DUAL-CHANNEL, 16-BIT, 250-MSPS ANALOG-TO-DIGITAL CONVERTER (ADC)

Technical Specifications

Parameters and characteristics for this part

SpecificationADS42JB69IRGCR
ArchitecturePipelined
ConfigurationS/H-ADC
Data InterfaceJESD204B
FeaturesSimultaneous Sampling
Input TypeDifferential
Mounting TypeSurface Mount
Number of A/D Converters2
Number of Bits16
Number of Inputs2
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Package / Case64-VFQFN Exposed Pad
Ratio - S/H:ADC1:1
Reference TypeInternal
Sampling Rate (Per Second)250 M
Supplier Device Package64-VQFN (9x9)
Voltage - Supply, Analog [Max]1.9 V
Voltage - Supply, Analog [Min]1.7 V
Voltage - Supply, Digital [Max]1.9 V
Voltage - Supply, Digital [Min]1.7 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTape & Reel (TR) 2000$ 223.85
Texas InstrumentsLARGE T&R 1$ 207.73
100$ 188.03
250$ 182.66
1000$ 179.08

Description

General part information

ADS42JB69 Series

The ADS42JB69 and ADS42JB49 are high-linearity, dual-channel, 16- and 14-bit, 250-MSPS, analog-to-digital converters (ADCs). These devices support the JESD204B serial interface with data rates up to3.125 Gbps. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy making it easy to drive analog inputs up to very high input frequencies. A sampling clock divider allows more flexibility for system clock architecture design. The devices employ internal dither algorithms to provide excellent spurious-free dynamic range (SFDR) over a large input frequency range.

The ADS42JB69 and ADS42JB49 are high-linearity, dual-channel, 16- and 14-bit, 250-MSPS, analog-to-digital converters (ADCs). These devices support the JESD204B serial interface with data rates up to3.125 Gbps. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy making it easy to drive analog inputs up to very high input frequencies. A sampling clock divider allows more flexibility for system clock architecture design. The devices employ internal dither algorithms to provide excellent spurious-free dynamic range (SFDR) over a large input frequency range.