ADS42JB69 Series
Dual-Channel, 16-Bit, 250-MSPS Analog-to-Digital Converter (ADC)
Manufacturer: Texas Instruments
Catalog
Dual-Channel, 16-Bit, 250-MSPS Analog-to-Digital Converter (ADC)
Key Features
• Dual-Channel ADCs14- and 16-Bit ResolutionMaximum Clock Rate: 250 MSPSJESD204B Serial InterfaceSubclass 0, 1, 2 CompliantUp to 3.125 GbpsTwo and Four Lanes SupportAnalog Input Buffer with High-Impedance InputFlexible Input Clock Buffer:Divide-by-1, -2, and -4Differential Full-Scale Input: 2 VPPand 2.5 VPP(Register Programmable)Package: 9-mm × 9-mm VQFN-64Power Dissipation: 850 mW/ChAperture Jitter: 85 fSrmsInternal DitherChannel Isolation: 100 dBPerformance:fIN= 170 MHz at 2 VPP, –1 dBFSSNR: 73.3 dBFSSFDR: 93 dBc for HD2, HD3SFDR: 100 dBc for Non HD2, HD3fIN= 170 MHz at 2.5 VPP, –1 dBFSSNR: 74.7 dBFSSFDR: 89 dBc for HD2, HD3 and95 dBc for Non HD2, HD3Dual-Channel ADCs14- and 16-Bit ResolutionMaximum Clock Rate: 250 MSPSJESD204B Serial InterfaceSubclass 0, 1, 2 CompliantUp to 3.125 GbpsTwo and Four Lanes SupportAnalog Input Buffer with High-Impedance InputFlexible Input Clock Buffer:Divide-by-1, -2, and -4Differential Full-Scale Input: 2 VPPand 2.5 VPP(Register Programmable)Package: 9-mm × 9-mm VQFN-64Power Dissipation: 850 mW/ChAperture Jitter: 85 fSrmsInternal DitherChannel Isolation: 100 dBPerformance:fIN= 170 MHz at 2 VPP, –1 dBFSSNR: 73.3 dBFSSFDR: 93 dBc for HD2, HD3SFDR: 100 dBc for Non HD2, HD3fIN= 170 MHz at 2.5 VPP, –1 dBFSSNR: 74.7 dBFSSFDR: 89 dBc for HD2, HD3 and95 dBc for Non HD2, HD3
Description
AI
The ADS42JB69 and ADS42JB49 are high-linearity, dual-channel, 16- and 14-bit, 250-MSPS, analog-to-digital converters (ADCs). These devices support the JESD204B serial interface with data rates up to3.125 Gbps. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy making it easy to drive analog inputs up to very high input frequencies. A sampling clock divider allows more flexibility for system clock architecture design. The devices employ internal dither algorithms to provide excellent spurious-free dynamic range (SFDR) over a large input frequency range.
The ADS42JB69 and ADS42JB49 are high-linearity, dual-channel, 16- and 14-bit, 250-MSPS, analog-to-digital converters (ADCs). These devices support the JESD204B serial interface with data rates up to3.125 Gbps. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy making it easy to drive analog inputs up to very high input frequencies. A sampling clock divider allows more flexibility for system clock architecture design. The devices employ internal dither algorithms to provide excellent spurious-free dynamic range (SFDR) over a large input frequency range.
