Zenode.ai Logo
Beta
74FCT162646ATPACT
Integrated Circuits (ICs)

SN74AVC16827DGG

Active
Texas Instruments

IC BUFF NON-INVERT 3.6V 56TSSOP

Deep-Dive with AI

Search across all available documentation for this part.

74FCT162646ATPACT
Integrated Circuits (ICs)

SN74AVC16827DGG

Active
Texas Instruments

IC BUFF NON-INVERT 3.6V 56TSSOP

Deep-Dive with AI

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74AVC16827DGG
Current - Output High, Low [custom]12 mA
Current - Output High, Low [custom]12 mA
Logic TypeBuffer, Non-Inverting
Mounting TypeSurface Mount
Number of Bits per Element10
Number of Elements2
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Output Type3-State
Package / Case6.1 mm
Package / Case0.24 in
Package / Case56-TFSOP
Supplier Device Package56-TSSOP
Voltage - Supply [Max]3.6 V
Voltage - Supply [Min]1.2 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyBulk 115$ 2.63

Description

General part information

SN74AVC16827 Series

A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical VOLvs IOLand VOHvs IOHcurves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive standard-output device. For more information, refer to the TI application reports,AVC Logic Family Technology and Applications, literature number SCEA006, andDynamic Output Control (DOCTM) Circuitry Technology and Applications, literature number SCEA009.

This 20-bit noninverting buffer/driver is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to 3.6-V VCCoperation.

The SN74AVC16827 is composed of two 10-bit sections with separate output-enable signals. For either 10-bit buffer section, the two output-enable (1OE1\ and 1OE2\ or 2OE1\ and 2OE2\) inputs must both be low for the corresponding Y outputs to be active. If either output-enable input is high, the outputs of that 10-bit buffer section are in the high-impedance state.

Documents

Technical documentation and resources

No documents available