Deep-Dive with AI
Search across all available documentation for this part.
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | CD74ACT373EG4 |
|---|---|
| Circuit [custom] | 8 |
| Circuit [custom] | 8 |
| Current - Output High, Low | 24 mA |
| Delay Time - Propagation | 3 ns |
| Independent Circuits | 1 |
| Logic Type | D-Type Transparent Latch |
| Mounting Type | Through Hole |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -55 °C |
| Output Type | Tri-State |
| Package / Case | 20-DIP |
| Package / Case | 7.62 mm |
| Package / Case | 0.3 in |
| Supplier Device Package | 20-PDIP |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 4.5 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
Description
General part information
SN74ACT373-EP Series
This 8-bit latch features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight latches are D-type transparent latches. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.
A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines in bus-organized systems without need for interface or pullup components.
Documents
Technical documentation and resources
No documents available
